Samsung Electronics Co., Ltd.

Arm Limited

Matthew Derrick Garrett

Hien Le

Vikas Sinha

Jiang Lin

Junhee Yoo

Robert Bell

Thomas H Hamilton

Manan Chugh

A memory controller includes a command scheduler, a timer and an interface configured to transmit memory access commands, including primary and secondary precursor memory access commands, to a memory. The command scheduler selects memory access commands associated with memory access requests. The timer indicates expiration of first and second time periods. The first time period is shorter than the second time period by a designated amount and the second time period is greater than or equal to a minimum time between a prior memory access command and a secondary precursor memory access command for the memory. The command scheduler allows selection of a primary precursor memory access command when the first time period has expired and allows selection of a secondary precursor memory access command when the second time period has expired.

Memory controller with speculative precursor commands

A system and a method provide a memory-access technique that effectively parallelizes DRAM operations and coherency operations to reduce memory-access latency. The system may include a memory controller, an interconnect and a processor. The interconnect may be coupled to the memory controller. The processor may be coupled to the memory controller through a first path and a second path in which the first path is through the interconnect and the second path bypasses the interconnect. The processor may be configured to send substantially concurrently a memory access request to the memory controller via the first path and send a page activation request or a hint request to the memory controller via the second path so that the DRAM access operations appear to be masked, or hidden by the coherency operations.

System and method for early DRAM page-activation

Efficiently tracking activations to rows of memory using a reduced number of row activation counters that indicate whether a memory row is activated during an activation period and row activation counters that indicate a number of permitted activations to a memory row within a maximum activation window.

Handling maximum activation count limit and target row refresh in DDR4 SDRAM

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Austin, TX, United States of America

Matthew Derrick Garrett