Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Sandisk Corporation

Matthew Davidson

Gary Lin

Daniel Edward Tuers

Eran Erez

Sergey Anatolievich Gorobets

Gautam Ashok Dusija

Yoav Weinberg

Mrinal Kochar

Michael Holtzman

Rajeev Nagabhirava

Paul A Lassa

Damian Pablo Yurzola

Reed P Tidwell

Asher Druck

Baruch Boris Cohen

Lakhdar Iguelmamene

Ramy Ayad

Nicholas Thomas

Robert Jackson

Ralph Heron

Muhammed Rijwane Ul Islam

Rony Tal

Systems and methods for redundant storage among networked video cameras are described. Video data for a group of video cameras is received by a parity video camera. The parity video camera calculates parity across the peer video data, stores the parity data to one storage location and backup video data for the storage location to another storage location. In some examples, the storage locations are selected from among the non-volatile memory of the group of video cameras or another group of video cameras.

Parity-based redundant video storage among networked video cameras

Systems, methods, and apparatus are provided that can reduce power consumption of memory controllers in response to memory command backlog in various situations. A data storage device includes a plurality of sets of non-volatile memory (NVM) devices, a central controller, and a plurality of channel controllers. Each channel controller is coupled to a distinct set of the plurality of sets of NVM devices. Each channel controller includes a command queue configured to store pending memory commands and provide backlog information. The central controller is configured to receive the backlog information of the command queues of the plurality of channel controllers, and adjust a clock frequency of the central controller and one or more clock frequencies of the plurality of channel controllers based on the backlog information such that the pending memory commands in each of the command queues are below a predetermined threshold level.

Reactive power management for non-volatile memory controllers

Systems and methods for storing data in a multi-level cell (MLC) flash memory are disclosed. One such data storage system has a data path with cascaded data access performance, including multiple storage portions having different data access speeds. A cascaded data path enables flash memory data access that has a more graceful degradation instead of an abrupt decrease in performance during operation.

Multi-level cell solid state device and method for transferring data between a host and the multi-level cell solid state device

The disclosure relates in some aspects to managing multi-tier memory, such as multi-tier NVM. Data that is originally written to a first tier (e.g., a fast tier) may be subsequently copied to a second tier (e.g., a slow tier). The data is temporarily left in the first tier until the space is needed for a subsequent write operation. Thus, for a period of time, a read operation is able to read the data from the first tier (e.g., the fast tier) instead of the second tier (e.g., the slow tier), thereby improving read performance. The disclosure relates in some aspects to a memory mapping scheme that enables a read operation to readily determine that data remains in the first tier and locate the data in that tier. Moreover, the scheme enables efficient reconfiguration of the mapping when the data in the first tier is erased.

Multi-tier memory management

A storage module may include a controller that has hardware path that includes a plurality of hardware modules configured to perform a plurality of processes associated with execution of a host request. The storage module may also include a firmware module having a processor that executes firmware to perform at least some of the plurality of processes performed by the hardware modules. The firmware module performs the processes when the hardware modules are not able to successfully perform them.

Hardware and firmware paths for performing memory read processes

A non-volatile memory system includes a memory controller that receives commands from a host and identifies commands that can be executed in parallel. The order in which commands are received is recorded so that responses may be provided to the host in the same order in which the commands were received.

Memory system with command queue reordering

Disclosed are apparatus and techniques for managing power in a memory system having a controller and nonvolatile memory array. In one embodiment, prior to execution of each command with respect to the memory array, a request for execution of such command is received with respect to the memory array. In response to receipt of each request for each command, execution of such command is allowed or withheld with respect to the memory array based on whether such command, together with execution of other commands, is estimated to exceed a predetermined power usage specification for the memory system.

Method and memory system for managing power based on semaphores and timers

The throughput of the memory system is improved where error correction of data in a data stream is cryptographically processed with minimal involvement of any controller. To perform error correction when data from the memory cells are read, the bit errors in the data in the data stream passing between the cells and the cryptographic circuit are corrected prior to any cryptographic process performed by the circuit. Preferably the error correction occurs in one or more buffers employed to buffer the data between the cryptographic circuit and the memory where latency is reduced by using multiple buffers.

Memory system with in stream data encryption/decryption and error correction

An interface for use of device whose core circuitry operates in one voltage domain, but exchanges signal with another device (or 'host') according a different voltage domain, and the use of such an interface for supplying data using a double data rate (DDR) transfer, is presented. One concrete example of this situation is a memory card, where the internal circuitry uses one voltage range for its core operating voltages, but exchanges signals with a host using different, input/output voltage range. According to a general set of aspects, the interface receives data signals from the device at the device's core operating voltage domain, individually level shifts these to the input/output voltage domain, and then combines them into a DDR signal for transfer to the host device, where a (non-level shifted) clock signal from the host device is used as the select signal to form the DDR data signal.

Growing community of inventors

Los Altos, CA, United States of America

Matthew Davidson