Qualcomm Incorporated

Matthew David Sienko

Ankit Srivastava

Peter J Shah

Jingxue Lu

Meysam Azin

Haibo Fei

Chenling Huang

Manu Mishra

Eugene Robert Worley

Sheng Zhang

Khosro Rabii

Francesco Gatta

Xiaohong Quan

Zhilong Tang

Iain Finlay

Weibo Hu

Joseph G Hamilton

A combined I/Q DAC is provided with a plurality of sources corresponding to a plurality of selectors in which the corresponding source drives the corresponding selector with a source signal to produce a corresponding pair of in-phase and quadrature-phase analog input signals to a summation network. Each selector routes its source signal responsive to a digital value of a corresponding in-phase and quadrature-phase bit pair.

Combined I/Q digital-to-analog converter

A switching mixer array is disclosed for the mixing of a digital LO signal with an analog input signal. Each switching mixer in the array is configured to assume either a first switching state or second switching state responsive to a respective bit of the digital LO signal.

Multiple element mixer with digital local oscillator synthesis

A system and method for pulse-width modulation (PWM) mismatch shaping. The method includes receiving a multi-bit pulse-code modulated (PCM) signal and generating a voltage ramp signal. The method includes generating a first corrected signal based on a first feedback signal and the multi-bit PCM signal. The method includes generating a first single-bit PWM signal based on the first corrected signal and the voltage ramp signal. The method includes delaying the voltage-ramp signal and generating a second corrected signal based on a second feedback signal and the multi-bit PCM signal. The method includes generating a second single-bit PWM signal based on the second corrected signal and the delayed voltage ramp signal and generating a multi-bit pulse-density modulation (PDM) signal based on the first single-bit PWM signal and the second single-bit PWM signal.

Delay-free poly-phase quantizer and quantization method for PWM mismatch shaping

A serial data receiver may include an edge detector and a digital integrator. The edge detector may be configured to provide one or more edge detection signals defining an edge detection indication in response to a comparison between two successive samples of a receiver input signal. The edge detection indication may represent a detected negative edge, a detected positive edge, or no detected edge. The digital integrator may be configured to provide a receiver output signal in response to integration of the one or more edge detection signals.

Differentiating-integrating sampling data receiver

A switching amplifier includes a compensation circuit to compensate for DC offset in the amplifier, to enhance operation of the switching amplifier. The compensation circuit may comprise a SAR ADC, where the DAC element can be used to provide a compensation voltage. The switching amplifier may further include a PWM modulator configured to avoid cross-talk to further enhance operation of the switching amplifier.

Audio switching amplifier

An apparatus includes voltage-to-current conversion circuitry comprising a first voltage-to-current converter and a second voltage-to-current converter. The apparatus also includes a capacitor coupled to the first voltage-to-current converter and to the second voltage-to-current converter.

Integrator for class D audio amplifier

One feature pertains to the synchronization of a serial time-division-multiplexed bus interconnecting an audio processing subsystem (i.e. a local node) with an audio coder-decoder (CODEC) subsystem (i.e. a remote node.) Control signals are transmitted along a bidirectional transmission line of the bus from the audio processing subsystem to the audio CODEC subsystem. The audio processing subsystem tracks an internal state machine phase count as the control signals are transmitted. The audio CODEC subsystem also tracks an internal state machine phase count as the signals are received. Transmission of control signals by the audio processing subsystem is periodically paused or suspended for a fixed interval of time based on the phase count to allow the audio CODEC subsystem to send a synchronization indicator signal back to the audio processing subsystem, which the audio processing subsystem uses to verify synchronization. This may be performed, for example, once every one hundred-twenty phase counts.

Serial time-division-multiplexed bus with bidirectional synchronization/control word line

A device includes a snapback clamp circuit configured to clamp a supply voltage in response to the supply voltage exceeding a trigger voltage level. In at least one embodiment, the snapback clamp circuit includes a clamp transistor and a programmable resistance portion that is responsive to a control signal to calibrate the trigger voltage level. Alternatively or in addition, the snapback clamp circuit may include a programmable bias device configured to calibrate the trigger voltage level by biasing a gate terminal of the clamp transistor. In another particular embodiment, a method of calibrating a snapback clamp circuit is disclosed. In another particular embodiment, a method of operating an integrated circuit is disclosed.

Devices and methods for calibrating and operating a snapback clamp circuit

In an aspect of the disclosure, a class D power amplifier with an overcurrent protection (OCP) circuit is provided. The class D power amplifier includes a plurality of output transistors, and the OCP circuit is mirrored to at least one output transistor of the plurality of output transistors in a closed-loop feedback configuration for precisely controlling a sensing current of the OCP circuit with respect to an output current of the at least one output transistor. The class D power amplifier with the OCP circuit in the closed-loop feedback configuration mitigates a variation in a current threshold value for triggering interruption of the class D power amplifier.

Overcurrent protection for class D power amplifier

Techniques for sensing current delivered to a load by a differential output stage, e.g., in a Class D amplifier. In one aspect, voltages across sense resistors coupled in series with first and second branches of the differential output stage are low-passed filtered and digitized. The sense resistors may be coupled in series with the sources of transistors of the first and second branches, wherein the transistors are selectively switchable on and off by input voltage driving voltages. The input driving voltages may correspond to a ternary voltage waveform such that during a given phase, the two transistors coupled in series with the sense resistors may be turned off. Further aspects provide for the first and second branches having cascoded NMOS and/or PMOS transistors, and the sense resistors being provided between a pair of cascoded transistors.

Load current sensing

A class D power amplifier is provided. The class D power amplifier includes a class D driver circuit having a plurality of output transistors, at least one active clamp circuit coupled to at least one output transistor of the plurality of output transistors, and at least one filter bank circuit coupled to the at least one active clamp circuit for controlling a voltage of the at least one output transistor. Accordingly, a voltage across a drain node and source node (VDS), a voltage across a gate node and source node (VGS), and a voltage across the gate node and drain node (VGD) of the output transistors is reduced to increase reliability of the power amplifier while consuming less power and utilizing less die area.

Split capacitors scheme for suppressing overshoot voltage glitches in class D amplifier output stage

Digital-to-analog converter circuitry is described. The digital-to-analog converter circuitry includes a plurality of weighted resistance elements. A first weighted resistance element includes a switch coupled to a reference voltage. The first weighted resistance element also includes a T-network coupled to the switch. The T-network approximately equalizes a first response speed of the first weighted resistance element with a response speed of a differently weighted resistance element.

Digital to-analog converter circuitry with weighted resistance elements

A digital-to-analog converter (DAC) includes a mismatch shaping feedback vector quantizer configured to store state information in expanded format using One-Hot Encoding of a matrix. The expanded state format storage enables implementation of a simplified state sorter for the vector feedback mechanism of the vector quantizer. The simplified state sorter may minimize the variance of ones (or other symbols representing state values) in the matrix, and allow performing sorting in a reduced number of clock cycles. For example, sorting may be performed on a predetermined edge of single clock cycle, or on two edges of the same clock cycle. The matrix may be normalized periodically or as needed, to avoid overflow and underflow. The DAC may be used as a quantizer of a modulator of an access terminal in a cellular communication system.

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San Diego, CA, United States of America

Matthew David Sienko