Cadence Design Systems, Inc.

Matthew David Eaton

Zhuo Li

George Simon Taylor

Ji Xu

Edward John Mottram

James Youren

Various embodiments provide for determining redundant logic in a circuit design based on one or more enable conditions of clock gates, which can be part of electronic design automation (EDA). In particular, some embodiments use one or more enable conditions (of the clock gates) with a satisfiability solver to determine redundant logic coupled to clock circuit elements gated by the clock gates.

Identifying redundant logic based on clock gate enable condition

Various embodiments provide for determining clock gates for decloning based on simulation and a satisfiability solver, which can be part of electronic design automation (EDA). In particular, some embodiments use a simulation process to quickly determine whether enable signals associated with two clock gates are logically equivalent using a random input vector to a circuit design and, if logically equivalent by the simulation process, use a satisfiability solver to determine a variable assignment (e.g., at least one vector) such that the enable signals are found to be non-equivalent.

Determining clock gates for decloning based on simulation and satisfiability solver

For a division of a dividend by a constant divider, a circuit architecture may calculate partial remainders. The circuit architecture may implement a tree structure to generate intermediate signals of partial remainders and combine adjacent intermediate signals to generate other partial remainders downstream. The circuit architecture may generate a quotient based on the partial remainders. The circuit architecture may also implement bit shifting and zero-padding on left side of the dividend to generate bit-level partial remainders. Furthermore, the circuit architecture may enable a fast round-to-zero division of signed integers by flipping the input bits of a negative integer and output bits of the corresponding quotient and performing only one increment operation, either before the division or after the division. In addition, the circuit architecture may also perform a division of a dividend in a carry-save form.

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Stow-cum-Quy, United Kingdom

Matthew David Eaton