Entropic Communications, Inc.

International Business Machines Corporation

Conexant Systems, Inc.

Trident Microsystems (far East) Ltd.

Brooktree Corporation

Matthew Damian Bates

Mark Alan Baur

Michael D Asal

David Cureton Baker

Jeffrey L Nye

Jonathan I Siann

Roderick Michael West

Paul B Wood

Lance G Hehenberger

Stephen G Glennon

Steven B Ehlers

A method, system and computer program for decompressing video data, storing the compressed video data in such a way that random access is possible and the data can be mapped efficiently into existing memory systems and interface protocols. The compression is accomplished via lossless compression using an algorithm optimized for video data. Due to the compressed format, data transmission consumes less bandwidth than using uncompressed data and prevents degradation in the decoded video.

Video decoder memory bandwidth compression

A device for transport stream processing is provided. The device includes a plurality of data inputs and a transport stream re-multiplexer for receiving a plurality of data streams from the plurality of data stream inputs and multiplexing the data streams into a transport stream. A transport stream processor receives the transport stream, de-multiplexes the transport stream to process one or more of the data streams, and provides the processed data stream to the transport stream re-multiplexer as one of the plurality of data streams.

Multi-format stream re-multiplexer for multi-pass, multi-stream, multiplexed transport stream processing

A system for encrypting and decrypting data is provided. The system includes a client for receiving a data packet, setting a value of a crypto bit, and transmitting the data packet over a system bus. A crypto module receives the data packet from the system bus and performs a cryptology function on the data packet based on a first value of the crypto bit. A memory controller receives the data packet from the system bus and performs non-cryptology functions on the data packet based on a second value of the crypto bit.

Encoded digital video content protection between transport demultiplexer and decoder

Embodiments of the invention comprise a new device and technique to realize an improved graphics generation system. This improvement is preferably achieved by implementing an interface logic portion to interface with the CPU, a control register portion, a pixel FIFO array portion, a pixel processing logic portion, and a control logic portion. These portions are preferably implemented as an extension of the internal architecture of the CPU. The CPU may be attached to the graphics system via a data cache and a write buffer portion. Data is read from the system memory and placed in the data cache so that subsequent accesses to the same location only require access to the cache. System memory data is written to a write buffer, so that the data written may be queued up and sent to the main memory at an appropriate time. The display refresh controller also reads the data from the system memory and converts the data to a signal for output to a display.

Microprocessor extensions for two-dimensional graphics processing

Multimedia information (e.g. graphics, video, sound, control information) passes through a system bus from a CPU main memory to a display memory in accordance with CPU commands. The information may be packetized with associated packet types identifying the different media. A media stream controller processes the information and passes the processed information to the display memory. Controllers in the media stream controller individually pass multimedia information to the display memory. A PACDAC controller in the media stream controller causes media (e.g. graphics, video) in the display memory to be transferred to a PACDAC for display. The format, sequence, and rate of this transfer may be flexibly controlled by software on a frame by frame basis. Arbitration logic establishes priorities for the different controllers in the media stream controller so they may share a single bus for accessing the display memory. A single interrupt controller coordinates interrupts (e.g. at a single level) to provide priorities based upon the type of interrupt cause or media. Each interrupt cause activates only the appropriate callback functions. Two different virtual machine sessions (e.g. Windows, DOS) share an interrupt line to process interrupt requests form one (1) session (e.g. Windows) before processing interrupt requests from the other.

Using prioritized interrupt callback routines to process different types

A Video-RAM semiconductor memory device comprised of a RAM army having an address input for inputting row, column, and target addresses, and a serial access array having a serial output port. The Video-RAM has address/control logic which detects a stimulus such as a RAS clock from an external controller indicating a coarse timing location for a data transfer between the RAM array and the serial access array. The control logic then provides control signals, that are internally synchronized with a serial clock, and that occur during a period that a tap pointer is equal to a value one less than a programmable target value or an input target address. This causes a row in the RAM array corresponding to an input row address to be transferred between the RAM array and the serial access array.

Growing community of inventors

Austin, TX, United States of America

Matthew Damian Bates