Hewlett-packard Development Company, L.p.

Hewlett Packard Enterprise Development LP

Intel Corporation

Valtrus Innovations Limited

Matthew D Pickett

Gilberto Medeiros Ribeiro

Jianhua Yang

Julien Borghetti

Richard Stanley Williams

John Paul Strachan

Frederick A Perner

Wei Yi

Janice H Nickel

Minxian Max Zhang

Dmitri Borisovich Strukov

Muhammad Shakeel Qureshi

Alexandre M Bratkovski

Warren Bruce Jackson

Philip John Kuekes

Wei Guang Wu

Perry Victor Lea

Alan Hersh Karp

Charles Santori

Gary Belgrave Gostin

Duncan R Stewart

Craig William Warner

Alan Lynn Davis

Hans S Cho

Terence Patrick Kelly

Qiangfei Xia

Kai-Mei Camilla Fu

Wojciech Golab

Duncan J Stewart

Jason M Seitz

Terrence P Kelly

R Stanley Williams

A system may intermittently illuminate a region, detect light from the intermittently illuminated region to form a detected signal, and process the detected signal with a demodulator. The demodulator may include a capacitor having an input to receive the detected signal, a resistor having an input connected to an output of the capacitor at a connection point, and a switch that connects the connection point to ground during times when the region is not illuminated. An output of the resistor may produce an output signal that is a high-pass filtered version of the detected signal during times when the region is illuminated, and a time-invariant ground signal during times when the region is not illuminated. Such a demodulator may reduce the effects of low-frequency noise sources, such as background light, op-amp offsets related to input bias, photodiode 1/f noise and dark current.

Demodulating a signal from intermittently illuminated region

Various systems and methods for implementing frequency domain adaptive motion cancellation filters. An example method includes receiving an optical signal representative of a physiological function. The example method further includes receiving a motion signal from an accelerometer. From the motion signal, a known motion spectrum is expressed as a sum of a product of coefficients for each component of the motion spectrum, wherein the coefficients are representative of the strength of the coupling between the motion signal and the optical signal. The example method may further include determining the coefficients of the motion spectrum using gradient descent and generating a decontaminated optical signal based on the optical signal and the motion model spectrum. Other systems, apparatuses, and methods are described.

Frequency domain adaptive motion cancellation filter

A neuristor-based reservoir computing device includes support circuitry formed in a complimentary metal oxide semiconductor (CMOS) layer, input nodes connected to the support circuitry and output nodes connected to the support circuitry. Thin film neuristor nodes are disposed over the CMOS layer with a first portion of the neuristor nodes connected to the input nodes and a second portion of the neuristor nodes connected to the output nodes. Interconnections between the neuristor nodes form a reservoir accepting input signals from the input nodes and outputting signals on the output nodes. A method for forming a neuristor-based reservoir computing device is also provided.

Neuristor-based reservoir computing devices

Shiftable memory employs ring registers to shift a contiguous subset of data words stored in the ring registers within the shiftable memory. A shiftable memory includes a memory having built-in word-level shifting capability. The memory includes a plurality of ring registers to store data words. A contiguous subset of data words is shiftable between sets of the ring registers of the plurality from a first location to a second location within the memory. The contiguous subset of data words has a size that is smaller than a total size of the memory. The memory shifts only data words stored inside the contiguous subset when the contiguous subset is shifted.

Shiftable memory employing ring registers

Word shift static random access memory (WS-SRAM) cell, word shift static random access memory (WS-SRAM) and method using the same employ dynamic storage mode switching to shift data. The WS-SRAM cell includes a static random access memory (SRAM) cell having a pair of cross-coupled elements to store data, a dynamic/static (D/S) mode selector to selectably switch the WS-SRAM cell between the dynamic storage mode and a static storage mode, and a column selector to selectably determine whether or not the WS-SRAM cell accepts shifted data. The WS-SRAM includes a plurality of WS-SRAM cells arranged in an array and a controller to shift data. The method includes switching a storage mode and activating a column selector of, coupling data from an adjacent memory cell to, and storing the coupled data in, a selected WS-SRAM cell.

Word shift static random access memory (WS-SRAM)

A shiftable memory supporting atomic operation employs built-in shifting capability to shift a contiguous subset of data from a first location to a second location within memory during an atomic operation. The shiftable memory includes the memory to store data. The memory has the built-in shifting capability. The shiftable memory further includes an atomic primitive defined on the memory to operate on the contiguous subset.

Shiftable memory supporting atomic operation

A method of shielding a memory device () from high write rates comprising receiving instructions to write data at a memory container (), the memory controller () composing a cache () comprising a number of cache lines defining stored data, with the memory controller (), updating a cache line in response to a write hit in the cache (), and with the memory controller (), executing the instruction to write data in response to a cache miss to a cache line within the cache () in which the memory controller () prioritizes for writing to the cache () over writing to the memory device ().

Cache line eviction based on write count

A shiftable memory is employed in a system and a method to shift a contiguous subset of stored data within the shiftable memory. The shiftable memory includes a memory having built-in shifting capability to shift a contiguous subset of data stored by the memory from a first location to a second location within the memory. The contiguous subset has a size that is smaller than a total size of the memory. The system further includes a processor to provide an address and the length of the contiguous subset. The method includes selecting the contiguous subset of data and shifting the selected contiguous subset.

Shiftable memory

A metal-insulator phase transition (MIT) flip-flop employs a selected one of a pair of bi-stable operating states to represent a logic state of the MIT flip-flop. The MIT flip-flop includes an MIT device having a current-controlled negative differential resistance (CC-NDR) to provide the pair of bi-stable operating states. A bi-stable operating state of the pair is capable of being selected by a programing voltage. Once the bi-stable operating state is selected, the bi-stable operating state is capable of being maintained by a bias voltage applied to the MIT device.

Metal-insulator phase transition flip-flop

A method of switching a memristive device applies a current ramp of a selected polarity to the memristive device. The resistance of the device during the current ramp is monitored. When the resistance of the memristive device reaches the target value, the current ramp is removed.

Method and circuit for switching a memristive device

Examples disclose a crossbar memory with a first crossbar to write data values corresponding to a word. The crossbar memory further comprises a second crossbar, substantially parallel to the first crossbar, to receive voltage for activation of data values across the second crossbar. Additionally, the examples of the crossbar memory provide an output line that interconnects with the crossbars at junctions, to read the data values at the junctions. Further, the examples of the crossbar memory provide a logic module to determine whether the second crossbar data values correspond to the word written in the first crossbar.

Crossbar memory to provide content addressable functionality

Apparatus and methods related to memory resistors are provided. A feedback controller applies adjustment signals to a memristor. A non-volatile electrical resistance of the memristor is sensed by the feedback controller during the adjustment. The memristor is adjusted to particular values lying between first and second limiting values with minimal overshoot. Increased memristor service life, faster operation, lower power consumption, and higher operational integrity are achieved by the present teachings.

Memory resistor adjustment using feedback control

Memristor systems and method for fabricating memristor system are disclosed. In one aspect, a memristor includes a first electrode, a second electrode, and a junction disposed between the first electrode and the second electrode. The junction includes at least one layer such that each layer has a plurality of dopant sub-layers disposed between insulating sub-layers. The sub-layers are oriented substantially parallel to the first and second electrodes.

Memristive devices with layered junctions and methods for fabricating the same

Memristors and their fabrication are provided. A first dielectric layer is formed over one or more conductive pathways. Vias are formed in the dielectric layer and filled with conductive material. A second dielectric layer is formed there over, and vias are formed aligned with and extending to the filled vias. A reactant fluid is introduced into the vias such that a reacted portion of the conductive material is defined within the filled vias. The vias in the second dielectric layer are then filled with conductive material such that memristors are defined. Conductive pathways are then formed over and in contact with the memristors such that each is individually addressable.

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San Francisco, CA, United States of America

Matthew D Pickett