Integrated Device Technology, Inc.

Rise Technology Company

Zettacom, Inc.

Matthew D Ornes

Gene K Chui

Christopher I W Norrie

Onchuen (Daryn) Lau

Robert James Divivier

Chris D Bergen

King-Shing (Frank) Chui

Chris Norrie

James Y Cho

Kenneth K Munson

Sean P Cummins

A programmably sliceable switch-fabric unit (PSSU) and methods of use are disclosed. An N&#xd7;N' switch matrix is programmably made to operate as if it were a plurality of S&#xd7;S&#x2032; virtual switch slices, where S&#x3c;N and S&#x2032;&#x3c;N&#x2032;. Ingressing requests each specify an egress path (unicast mode) or plural egress paths (multicast mode) in terms of one or more relative egress port numbers. A request translator converts relative egress port numbers into absolute egress port numbers by determining what virtual slice each request belongs to. The translated egress requests are handed off to an arbitration and/or scheduling mechanism for further processing. If the translated request is granted, the corresponding payload egresses through the actual egress port(s) which the translated request asked for. An inventory of PSSU's may be distributed in accordance with the disclosure to segmented markets such that each PSSU can service the specific needs of a market, be it providing a plurality of 4&#xd7;4 switch slices, 8&#xd7;8 switch slices, 16&#xd7;16 switch slices, or otherwise. In one embodiment, virtual slices are distributed throughout a physical switch-matrix so as to minimize pinout crossover for external line card units.

Programmably sliceable switch-fabric unit and methods of use

A system and method in accordance with the invention produces an ECC code that is transmitted in the y-bit domain along with data is converted from a native x-bit domain to the y-bit domain. Such a system and method provides a representation of an ECC code that is part of a transmitted serial stream that allows clock recovery and that can use parity checking or other method to verity the integrity of the transmitted ECC code itself.

Method and system for error correction over serial link

In a system having independently-clocked job-performing circuits (e.g., payload processors) and independently-clocked job-ordering circuits (e.g., request and payload suppliers), coordinating mechanisms are provided for coordinating exchanges between the independently-clocked circuits. The coordinating mechanisms include those that use transmitted time-stamps for scheduling contention-free performances within the job-performing circuits of requested jobs. The coordinating mechanisms additionally or alternatively include static and dynamic rate constraining means that are configured to prevent a faster-clocked one of the independently-clocked circuits from overwhelming a more slowly-clocked other of the independently-clocked circuits. In one implementation, independently-clocked telecommunication-shelves house a distributed set of line cards and switch cards. An asynchronous interconnect is provided between the independently-clocked shelves for carrying job requests and payload data between the distributed line cards and the distributed switch cards. The multi-shelf system is scalable and robust because additional or replacement line and switch cards may be inserted into one or another of the independently-clocked shelves as desired and because a unified clock-tree is not needed for synchronizing activities within the interconnected, but independently clocked shelves.

Variably delayable transmission of packets between independently clocked source, intermediate, and destination circuits while maintaining orderly and timely processing in one or both of the intermediate and destination circuits

A digital switching system comprises: (a) a line card layer containing a plurality of real or virtual line cards; (b) a switch card layer containing a plurality of real or virtual switch cards; and (c) an interface layer interposed between the line card layer and the switch card layer for providing serialization support services so that one or more of the line cards and switch cards can be operatively and conveniently disposed in a first shelf or on a first backplane that is spaced apart from a second shelf or from a second backplane supporting others of the line cards and/or switch cards. Such an arrangement allows for scalable expansion of the switching system in terms of number of lines served and/or transmission rates served. The flexibility of the system is owed in part to payload data being carried within payload-carrying regions of so-called ZCell signals as the payload data moves between the line card layer and the switch fabric layer.

Multiservice switching system with distributed switch fabric

A method and apparatus for scheduling static and dynamic traffic through a switch fabric are described. The method comprises for each switch slice in a distributed switch fabric, scheduling static traffic by reserving time slots for transmission of the static traffic to at least one destination, and scheduling dynamic traffic so as not to be transmitting the dynamic traffic to the at least one destination during the reserved time slots. The apparatus implements the method and comprises a memory storing a schedule of static traffic, shifters storing dynamic traffic scheduling requests, and a grant scheduler.

Method and apparatus for scheduling static and dynamic traffic through a switch fabric

An apparatus and method for reordering sequence indicated information units into proper sequence are described. The apparatus includes a double-back shifter receiving sequence indicated information units, and at least one circuit coupled to the double-back shifter to repetitively compare, reorder and shift the sequence indicated information units so as to be in proper sequence when shifted out of the double-back shifter. The method includes repetitively comparing, reordering and shifting sequence indicated information units in a double-back shifter so as to be in proper sequence when shifted out of the double-back shifter.

Apparatus and method for reordering sequence indicated information units into proper sequence

A system and method in accordance with the invention produces an ECC code that is transmitted in the y-bit domain along with data that is converted from a native x-bit domain to the y-bit domain. Such a system and method provides a representation of an ECC code that is part of a transmitted serial stream that allows clock recovery and that can use parity checking or other method to verify the integrity of the transmitted ECC code itself.

A write buffer unit operates in a cached memory microprocessor system by dynamically reconfigurable timed flushing of a queue of coalescing write buffers in the unit. Each time an additional one of the coalescing write buffers is allocated, a time-out period is generated which is inversely related to the number of allocated write buffers. After one of the allocated write buffers times out by exceeding the time-out period with no write activity to the coalescing write buffer, a controller in the unit determines the least recently written to allocated write buffer, and generates control signals to flush that write buffer.

Apparatus and method for dynamically reconfigurable timed flushing of a queue of coalescing write buffers

A technique and system for reading instruction data from a cache memory with minimum delays. Addresses are calculated and applied to the cache memory in two or more cycles by a pipelined address generation circuit. While data at one address is being retrieved, the next address is being calculated. It is presumed, when calculating the next address, that the current address will return all the data it is addressing. In response to a miss signal received from the cache when no data at the current address is in the cache, the missed data is read from a main system memory and accessed with improved speed. In a system where the cache memory and processor operate at a higher clock frequency than the main system memory, new data is obtained from the main memory during only periodically occurring cache clock cycles. A missed cache memory address is regenerated in a manner to access such new data during the same cache clock cycle that it first becomes available from the main memory. This eliminates the occurrence of penalty delay cycles that reduce the rate at which instructions are issued in existing processors, and thus improves the speed of operation of the processors.

Growing community of inventors

Madison, WI, United States of America

Matthew D Ornes