Intel Corporation

Intel Corparation

Matthew C Merten

Ravi Rajwar

Martin Guy Dixon

Konrad K Lai

Beeman C Strong

Alexandre J Farcy

Bret L Toll

Tong Li

James Hadley

Per H Hammarlund

Srikanth T Srinivasan

Bratin Saha

Avinash Sodani

Michael W Chynoweth

Morris Marden

Justin M Deinlein

Jason W Brandt

Stanislav Viktorovich Bratanov

Vijaykumar Balaram Kadgi

Ilhyun Kim

Ahmad Yasin

Seth Abraham

Andreas Kleen

Suresh Srinivas

Laura A Knauth

Kimberly C Weier

Angela D Schmid

Christine E Wang

Kshitij Arun Doshi

Hong Wang

Gad Shlomo Sheaffer

Quinn Able Jacobson

Robert S Chappell

John P Shen

Rajesh S Parthasarathy

Anupama Suryanarayanan

Ryan Carlson

Mark Dechene

Ammon J Christiansen

Grant G Zhou

Yury N Ilin

Prakash Math

Anne Weinberger Bracy

Bambang Sutanto

Vinodh Gopal

Gilbert M Wolrich

Wajdi K Feghali

James D Guilford

Ali-Reza Adl-Tabatabai

Stephen H Gunther

Erdinc Ozturk

Gautham N Chinya

Sean Mirkes

Ofer Levy

Frank Binns

Peter Lachner

Sebastien Hily

Peggy J Irelan

Mayank Bomb

Iredamola Dammy Olopade

Thilo Schmitt

Joseph A McMahon

Seung-Woo Kim

Chia Yin Kevin Lai

Gilbert A Neiger

Glenn J Hinton

Wei Wang

Stephan Jourdan

Kun Tian

Koichi Yamada

David A Koufaty

Ronak Singhal

Paul Caprioli

Jonathan D Combs

Abhay Kanhere

John G Holm

Jason M Agron

David W Burns

Itamar S Kazachinsky

Omar M Shaikh

Muawya M Al-Otoom

Jeremy R Anderson

Ali-Reza Adi-Tabatabai

Vivek Thakkar

Thomas F Toll

Md Asifur Rahman

Charlie J Hewett

Santhosh Srinath

Kan Liang

Thomas Toll

Rahul R Kulkarni

Ilya Wagner

Grace C Lee

Fariborz Tabesh

Pawel Osciak

James D Hadley

David Lim

Hugh M Caffey

Gautham Shinya

Bratin Saba

In an embodiment, a processor for redirecting requests includes a processing engine to execute a guest system, and monitoring circuitry coupled to the processing engine. The monitoring circuitry may be to: receive, from the guest system, a first request to access a first virtual counter; in response to a receipt of the first request, determine, based a mapping register of the processor, a first physical counter mapped to the first virtual counter; and redirect the first request to the first physical counter mapped to the first virtual counter. Other embodiments are described and claimed.

Processor including monitoring circuitry for virtual counters

A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register.

Addition instructions with independent carry chains

A method for tracing software code executing on a core of a processor is described. The method includes generating a set of packets for a trace packet stream based on a main cycle counter, which maintains a count of cycles elapsing in the core since a packet was emitted into the trace packet stream, and a commit cycle counter, which maintains a cycle count in the core since the last commit operation, wherein the generating comprises (1) storing a value of the main cycle counter in the commit cycle counter in response to detecting a commit operation and (2) storing a value of the commit cycle counter in the main cycle counter in response to detecting an abort in the core; and emitting the set of packets from the processor into the trace packet stream for tracing execution of the software code.

Trace management during aborted speculative operations

A processor is to execute and retire instructions for a virtual machine. A reload register is coupled to the core is to store a reload value. A performance monitoring counter (PMC) register is coupled to the reload register and an event-based sampler operatively is coupled to the reload register and the PMC register. The event-based sampler includes circuitry to load the reload value into the PMC register and increment the PMC register after detecting each occurrence of an event of a certain type as a result of execution of the instructions. Upon detecting an occurrence of the event after the PMC register reaches a predetermined trigger value, the event-based sampler is to execute microcode to generate field data for elements within a sampling record, wherein the field data relates to a current processor state of execution, and reload the reload value from the reload register into the PMC register.

Virtualizing precise event based sampling

A processor and method are described for a multi-level reservation station. For example, one embodiment of an apparatus comprises: execution circuitry comprising a plurality of functional units to execute a plurality of operations; a reservation station comprising a plurality of entries to store a corresponding plurality of operations to be executed on one or more of the functional units, the reservation station comprising: a first RS level to hold a first subset of the plurality of operations which are ready for execution by one or more functional units or which are expected to be ready for execution by the functional units; a second RS level to hold a second subset of the plurality of operations which are not expected to be ready for execution by the functional units; operation evaluation circuitry to evaluate operations in the first RS level and, responsive to identifying one or more operations which are not expected to be ready for execution, to cause the one or more operations to be moved from the first RS level to the second RS level.

Method and apparatus for a multi-level reservation station with instruction recirculation

An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software. And to enable testing of such a fallback path, in one implementation, hardware provides software a mechanism to always abort speculative code regions.

Apparatus and method for transactional memory and lock elision including abort and end instructions to abort or commit speculative execution

Apparatus and method for transactional memory and lock elision including an abort instruction to abort speculative execution

In accordance with embodiments disclosed herein, there is provided systems and methods for tracking the mode of processing devices in an instruction tracing system. The method may include receiving an indication of a change in a current execution mode of the processing device. The method may also include determining that the current execution mode of the received indication is different than a value of an execution mode of a first execution mode (EM) packet previously-generated by the IT module. The method may also include generating, based on the determining that the current execution mode is different, a second EM packet that provides a value of the current execution mode of the processing device to indicate the change in the execution mode for an instruction in a trace generated by the IT module. The method may further include generating transactional memory (TMX) packets having n bit mode pattern in the packet log. The n is at least two and the n bit mode indicates transaction status of the TMX operation.

Tracking mode of a processing device in instruction tracing systems

Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.

Instruction and logic to test transactional execution status

In one embodiment, a processor includes a performance monitor including a last branch record (LBR) stack to store a call stack to an event of interest, where the call stack is collected responsive to a trigger for the event. The processor further includes logic to control the LBR stack to operate in a call stack mode such that an entry to a call instruction for a leaf function is cleared on return from the leaf function. Other embodiments are described and claimed.

Method and apparatus for obtaining a call stack to an event of interest and analyzing the same

A scheduler implementing a dependency matrix having restricted entries is disclosed. A processing device of the disclosure includes a decode unit to decode an instruction and a scheduler communicably coupled to the decode unit. In one embodiment, the scheduler is configured to receive the decoded instruction, determine that the decoded instruction qualifies for allocation as a restricted reservation station (RS) entry type in a dependency matrix maintained by the scheduler, identify RS entries in the dependency matrix that are free for allocation, allocate one of the identified free RS entries with information of the decoded instruction in the dependency matrix, and update a row of the dependency matrix corresponding to the claimed RS entry with source dependency information of the decoded instruction.

Scheduler implementing dependency matrix having restricted entries

Growing community of inventors

Hillsboro, OR, United States of America

Matthew C Merten