Hewlett-packard Development Company, L.p.

Matthew C Mattina

Shane Bell

Bongjin Jung

Judson S Leonard

Matthew H Reilly

Chuan-Hua Chang

Carl Geisler Ramey

Each processor in a distributed shared memory system has an associated memory and a coherence directory. The processor that controls a memory is the Home processor. Under certain conditions, another processor may obtain exclusive control of a data block by issuing a Load Lock instruction, and obtaining a writeable copy of the data block that is stored in the cache of the Owner processor. If the Owner processor does not complete operations on the writeable copy of the data prior to the time that the data block is displaced from the cache, it issues a Victim To Shared message, thereby indicating to the Home processor that it should remain a sharer of the data block. In the event that another processor seeks exclusive rights to the same data block, the Home processor issues an Invalidate message to the Owner processor. When the Owner processor is ready to resume operation on the data block, the Owner processor again obtains exclusive control of the data block by issuing a Read-with Modify Intent Store Conditional instruction to the Home processor. If the Owner processor is still a sharer, a writeable copy of the data block is sent to the Owner processor, who completes modification of the data block and returns it to the Home processor with a Store Conditional instruction.

Mechanism for handling load lock/store conditional primitives in directory-based distributed shared memory multiprocessors

A multi-threaded processor is configured to detect excepted instructions from a first program, and to stop fetching younger instructions from that same program, to thereby conserve system resources that can be used by other programs. Each fetched program instruction has an associated status bit, which is set if the instruction excepts. Each excepting instruction is logged in an exception logging unit, which causes the associated status bit to be set. Each program has an associated in-flight vector table that tracks the instructions that have been fetched for that program. The status bits are compared with the in-flight vector table to identify the program that is associated with an excepted instruction. That program is then disabled, thereby preventing further fetching of instructions for that program until the excepted instruction clears.

System and method to avoid resource contention in the presence of exceptions

An exception handler for a processor is split into two functional units to permit exceptions to be classified into two categories. The first category of exceptions includes performance critical excepted instructions, while the second category includes non-performance critical excepted instructions. The performance critical exceptions are routed to a speculative exception handler, which resolves the exceptions speculatively, even though the excepted instruction may lie in a speculative path of the program flow. The non-performance critical exceptions are routed to a non-speculative exception handler that only resolves exceptions when the excepted instruction is certain to execute in an actual path of the program flow.

Growing community of inventors

Hudson, MA, United States of America

Matthew C Mattina