National Instruments Corporation

Qualcomm Incorporated

Matthew C Curtis

Jacob Kornerup

Aljosa Vrancic

Steve Rogers

Biren Shah

Jeffrey N Correll

Matthew E Novacek

Timothy J Hayles

Christopher Frederick Graf

Sergei Larin

Adam K Gabbert

James M Lewis

Anshuman Das Gupta

Ariane M Chan-You

Jenifer M Loy

Ron Lieberman

Amanda E Cruess

Jayson P Ryckman

An example system for compiling a source file includes an optimizer that identifies a segment of code in a first source file as a potential optimization opportunity. The first source file includes high-level source code. The example system also includes a compiler that identifies a compilation record storing data indicating that the segment of code is an actual optimization opportunity and generates a representation of the high-level source code in accordance with the actual optimization opportunity. The data is based on a previous compilation of a second source file.

Whole-program optimization using data from previous compilation runs

A system and method for configuring objects in a system diagram to access interfaces of other objects are described. A first node and a second node may be displayed in the system diagram. The second node may implement one or more interfaces, where each interface includes one or more callable functions. An interface wire connecting the first node to the second node may be displayed in response to user input. The system may automatically configure the first node to access at least one of the one or more interfaces of the second node in response to displaying the interface wire.

Interface wires for a measurement system diagram

Displaying physical signal routing of a system. A diagram of the system may be displayed. The system may include physical components connected via physical connections and logical components implemented on various ones of the physical components. The diagram may include a plurality of icons connected by wires. At least a first subset of the icons may represent logical elements of the system and wires between the first subset of icons may represent logical connections between corresponding logical elements. User input requesting signal routing information of the system may be received. In response, a signal route corresponding to a first logical connection between a first logical element and a second logical element may be visually indicated.

Displaying physical signal routing in a diagram of a system

A system and method for creating a graphical program. A function block may be displayed in a graphical program. The graphical program may include a plurality of interconnected blocks which visually indicate the functionality of the program. Additionally, the function block may be operable to perform a first function and may include one or more inputs and one or more outputs. User input specifying an attribute behavior for the function block may be received, e.g., via a menu which allows selection or definition of attribute behaviors, a graphical wizard, or another graphical program, among other methods. The attribute behavior specified for the function block may be usable to determine at attribute of at least a subset of the one or more outputs of the function block based on an attribute of at least one of the one or more inputs to the function block.

System and method for enabling a graphical program to propagate attributes of inputs and outputs of blocks

A 'timed loop with frames' node may be included in a graphical program. The 'timed loop with frames' node may combine a timed loop with a timed sequence such that the timed sequence is executed at each iteration of the timed loop. The &#x201c;timed loop with frames&#x201d; node may be configured with first execution timing information that controls execution timing for the iterations of the loop. A plurality of graphical code portions may be included in the &#x201c;timed loop with frames&#x201d; such that a sequential order of execution for the graphical code portions is specified. The &#x201c;timed loop with frames&#x201d; node may be configured with second execution timing information that controls execution timing for the graphical code portions executed at each iteration.

Timed loop with sequence frames structure for a graphical program

A combination structure node is provided by a graphical programming development environment for use in a graphical program, where the combination structure node is operable to perform two or more control flow functions. For example, the combination structure node may be operable to perform two or more of: iteration, looping, conditional branching, sequencing, timed execution, event-driven execution, or other control flow functions. A user may include the combination structure node in a graphical program and associate a graphical code portion with the combination structure node. During execution of the graphical program, the combination structure node is operable to cause the associated graphical code portion to execute according to the two or more control flow functions performed by the combination structure node.

Combination structure nodes for a graphical program

A pattern may be written to an allocated section of host memory to track how much data has been received in the host memory from a direct memory access controller coupled to a First In, First Out memory. A driver may send the most recently written sample of data from the host memory to an application requesting sampled data. The driver may determine the amount of data written to the host memory by reading the allocated section of host memory and determining the size of a portion of memory, that previously had the pattern, that has been written over with data. The driver may determine if more data than a predetermined amount of data has been written to the host memory or is available to be written to the host memory, and if necessary, send an indication to the application.

Growing community of inventors

Austin, TX, United States of America

Matthew C Curtis