Intersil Americas Inc.

Harris Corporation

North Carolina State University

Square D Company

Renesas Electronics America Inc.

Matthew Burdet Harris

Michael M Walters

Bogdan M Duduman

Robert H Isham

Steven Patrick Laur

Rhys S A Philbrick

Chun Cheung

Anthony Clement Manicone

Weihong Qiu

Thomas Andrew Jochum

Kunrong Wang

Jian Yin

Charles Edward Hawkes

Brandon Day

James William Leith

Arthur W Kelley

Paul Dackow

Brandon Howell

Methods and apparatuses for controlling an apparatus comprising a controller integrated in a first slave device. In an example, the controller can detect a sensed current of the first slave device. The controller can receive a voltage signal associated with a second slave device connected to the first slave device. The controller can generate a correction current based on the sensed current of the first slave device and the voltage signal. The controller can modulate a pulse width modulation (PWM) signal received by the first slave device using the correction current. The controller can control a power converter using the modulated PWM signal.

Integrated current sharing schemes for multiplying power stages support of a multiphase controller

An embodiment of a power-supply module includes a molded package, power-supply components disposed within the package, and an inductor disposed within the package and over the power-supply components. For example, for a given output-power rating, such a power-supply module may be smaller, more efficient, and more reliable than, and may run cooler than, a power-supply module having the inductor mounted outside of the package or side-by-side with other components. And for a given size, such a module may have a higher output-power rating than a module having the inductor mounted outside of the package or side-by-side with other components.

Molded power-supply module with bridge inductor over other components

A switching regulator and controller and an electronic device using same are disclosed in which the controller includes a sense circuit, an error amplifier circuit, a filter and reference circuit, and a comparator circuit. The switching regulator includes a pulse switch circuit coupled to an output inductor for developing an output voltage. The sense circuit provides a sense signal indicative of current through the output inductor. The error amplifier circuit develops an error signal indicative of error of the output voltage. The filter and reference circuit high pass filters the sense signal to provide a filtered sense signal and which balances the filtered sense signal and the error signal at a common DC level. The comparator circuit develops a pulse control signal using the error signal and the filtered sense signal, where the pulse control signal is for controlling switching of the pulse switch circuit.

Switching regulator with balanced control configuration with filtering and referencing to eliminate compensation

A controller for a switching regulator is disclosed including a sense circuit, an error amplifier circuit, a filter and reference circuit, and a comparator circuit. The switching regulator includes a pulse switch circuit coupled to an output inductor for developing an output voltage. The sense circuit provides a sense signal indicative of current through the output inductor. The error amplifier circuit develops an error signal indicative of error of the output voltage. The filter and reference circuit high pass filters the sense signal to provide a filtered sense signal, and references the filtered sense signal and the error signal to a common DC level. The comparator circuit develops a pulse control signal used to control switching of the pulse switch circuit based on comparing the error signal with the filtered sense signal.

A DC-to-DC converter includes one or more power switches, a pulse width modulation circuit for generating control pulses for the power switches, and an output inductor connected to the power switches. A thermally compensated current sensor is connected to an intrinsic current sensing element exhibiting a temperature-based parameter non-linearity. The thermally compensated current sensor has a temperature coefficient that substantially matches a temperature coefficient of an intrinsic power converter element used to measure current flow, thus linearizing the current measurement. Also, a current feedback loop circuit cooperates with the pulse width modulation circuit to control the power switches responsive to the thermally compensated current sensor.

Thermally compensated current sensing of intrinsic power converter elements

RF amplifier bias system for TDMA application. A bias circuit () is coupled to an RF power amplifier () circuit. The bias circuit includes a charge pump/sink circuit () a voltage reference circuit () and voltage scaling circuit (). The bias system provides fast response time when transitioning between various bias voltage applied to an FET RF transistor ().

Fast bias for power amplifier gating in a TDMA application

An apparatus for improved grounding and heat transfer between flange mount field effect transistors and printed wiring boards is provided comprising a cut-out formed in the printed wiring board, extending between its top and bottom surfaces, defining an edge which is covered or plated with a conductive material at least in some areas. One or more vias also extend between the top and bottom surfaces of the cut-out and are exposed along the edge. A field effect transistor is placed in the cut-out and into contact with a heat sink element designed to enhance grounding of the field effect transistor and improve the transfer of heat to the chassis or other metal support structure for the printed wiring board.

Apparatus for improved grounding of flange mount field effect transistors to printed wiring boards

A semi-clockless, cascaded, current-mode regulator has a first regulator that receives a clock signal from a controller. By 'semi-clockless' is meant that a clock signal is applied to the first of a cascaded plurality of regulators, and that as a result of the cascading of clock delay circuits in each of the regulators, the remaining regulators receive sequentially delayed versions of the clock signal applied to the first regulator. The regulators are coupled to control the operations of associated pulse width modulation controlled switching circuits. Outputs of the switching circuits are combined to realize a multi-phase output voltage.

Semi-clockless, cascaded, current-mode power regulator having high noise immunity and arbitrary phase count

A PWM system that minimizes output ripple of a multiphase DC-DC converter which converts N input voltages including at least one dissimilar input voltage. The PWM system includes PWM waveform logic that generates N PWM signals including a PWM signal for each of the N input voltages, and PWM control logic that optimizes relative phases of the N PWM signals based on voltage levels of the N input voltages. Various circuits and/or methods are contemplated for optimizing phase, including, for example, centering pulses for each PWM cycle, distributing pulses based on predetermined optimal phase angles, determining input voltage levels and selecting predetermined optimal phase angles, generating phase signals employing predetermined phase angles, measuring input voltages and calculating optimal phase angles, and using PLL logic or the like to measure and equalize off-times between PWM pulses.

Multiphase DC-DC converter with reduced ripple

A cascadable power regulator including a programmable delay unit and PWM control logic. The programmable delay unit initiates a delay period in response to a digital input signal and asserts a digital output signal upon expiration of the delay period. The PWM control logic controls a PWM cycle in response to the digital input signal and in response to an output control condition. The cascadable regulator uses digital signals to communicate between channels. Digital signals are not prone to the same kind of signal degradation or noise susceptibility as analog signals. Thus, the number of phases is not limited, the physical separation between the regulators is not limited, and the switching frequency is not as limited. There is no clock signal from a separate controller so that the controller is a relatively simple, low-cost device. Since there is no clock, a unique self-oscillating system is achieved using the cascadable regulator.

Cascadable current-mode regulator

A reduced pin count, dual channel driver interface is configured to interface a supervisory controller with a plurality of multi-phase output channel switching circuits of a multi-phase DC-DC regulator. Each dual channel driver is configured for placement relatively close to output channel sense points, so as to effectively reduce the distance that would otherwise have to be traversed by noise sensitive voltage signals. Sensed current representative signals are processed within the dual driver for current balance between a respective multi driver pair, and are combined to supply the controller with the average current signal of the dual channels. The controller uses this average current-information to adjust respective pulse width modulation signals that are supplied to the dual channel drivers.

Multi-channel driver interface circuit for increasing phase count in a multi-phase DC-DC converter

A clocked cascadable power regulator including synchronization logic and PWM control logic. The synchronization logic receives a clock signal and asserts a digital output signal synchronized with the clock signal in response to assertion of a digital input signal. The PWM control logic controls a PWM cycle in response to the digital input signal and in response to an output control condition. The regulator may be used alone or cascaded with other similar regulators for implementing a multiphase power converter with multiple channels. The clocked cascadable regulator uses digital signals to communicate between channels. Digital signals are not prone to the same kind of signal degradation or noise susceptibility as analog signals. In the cascaded configuration, there is one clock common to all channels which ensures that the phase separation between the channels is symmetrical to within the jitter tolerance of the common clock.

Clocked cascading current-mode regulator with high noise immunity and arbitrary phase count

A multi-phase DC&#x2014;DC converter architecture in which parameters including error signal gains and modulator gains are defined so as to balance multiple converter channel currents, irrespective of whether the converter channels are supplied with the same or different input voltages.

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Durham, NC, United States of America

Matthew Burdet Harris