Silicon Laboratories Inc.

Matthew Brandon Gately

Eric Jonathan Deal

Mark Willard Johnson

Daniel Thomas Riedler

Sebastian Ahmed

Øivind Aleksander Grimsgaard Loe

An apparatus includes an array processor to process array data in response to information contained in a packet, wherein the packet comprises a set of fields specifying configuration information for processing the array.

Apparatus for array processor with program packets and associated methods

An apparatus includes an array processor to process array data in response to a set of macro-instructions. A macro-instruction in the set of macro-instructions performs loop operations, array iteration operations, and/or arithmetic logic unit (ALU) operations.

Processor with macro-instruction achieving zero-latency data movement

An apparatus includes an array processor to process at least one array. The apparatus further includes a memory coupled to the array processor. The at least one array is stored in memory with programmable per-dimension size and stride values.

Array processor using programmable per-dimension size values and programmable per-dimension stride values for memory configuration

An apparatus includes an array processor to process array data. The array data are arranged in a memory. The array data are specified with programmable per-dimension size and stride values.

Array processor having an instruction sequencer including a program state controller and loop controllers

A method includes, in response to a master port requesting bus access for a bus transfer with a slave port, selecting the master port to allow a master device that is coupled to the master port to perform a bus transfer with a slave device that is coupled to the slave port. The bus transfer is associated with at least one bus cycle. The method includes, in response to an end of the bus transfer, maintaining selection of the master port for at least one additional bus cycle.

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Austin, TX, United States of America

Matthew Brandon Gately