Seagate Technology Incorporated

Hewlett-packard Development Company, L.p.

Matthew B Lovell

Thomas V Spencer

Daniel John Benjamin

David W Claude

Ryan James Goss

Stacey Secatch

Pavel Vasek

Jon David Trantham

Darel N Emmot

Steven Scott Williams

Mohamad H El-Batal

Derek Alan Sherlock

Jonathan Kent Ross

Patrick Knebel

Leith L Johnson

Kevin Lee Van Pelt

Stephen H Perlmutter

Joe Perry Cowan

James Robert Peterson

David Jerome Allen

The technology disclosed herein provides a memory blade including a plurality of fabric switches configured to receive commands from a plurality of host clients, an address decoder and tracker circuit communicatively connected to the fabric switches and configured to determine the source of commands received at the fabric switches an aggregator crossbar configured to provide bandwidth aggregation between host clients and a plurality of memory modules; and a buffer module configured to couple the commands from the plurality of host clients with the plurality of memory modules.

Fault-tolerant memory appliance

A data storage system may have a plurality of memory cells located in different data storage devices that are arranged into a plurality of logical namespaces with each logical namespace configured to be sequentially written and entirely erased as a single unit. An asymmetry strategy may be proactively created with the asymmetry module in response to data access activity to the logical namespaces by the asymmetry module. A new mode, as prescribed by the asymmetry strategy, is entered for at least one logical namespace in response to an operational trigger being met. The new mode changes a timing of at least one queued data access request to at least one logical namespace.

Data storage system with workload-based asymmetry compensation

A data storage system may have a data storage device with a memory arranged into a plurality of logical namespaces. A power module can be connected to the plurality of logical namespaces and configured to transition at least one memory cell in response to a workload computed for a namespace of the plurality of the logical namespaces to maintain a power consumption of 8 watts or less for the data storage device.

Data storage system with workload-based dynamic power consumption

A system can log data access activity to a memory array with a metadata module while the memory array is logically divided into multiple namespaces. A workload can be determined for each namespace by the metadata module and a metadata strategy can be created with the metadata module in view of the respective namespace workloads. A first metadata and second metadata may be generated for respective first and second user-generated data for storage into a first namespace of the multiple namespaces. The first metadata can be compressed with a compression level prescribed by the metadata strategy in response to a detected or predicted workload to the first namespace before the first metadata, second metadata, first user-generated data, and second user-generated data are each stored in the first namespace.

Lossless namespace metadata management system

Method and apparatus for managing data buffers in a data storage device. In some embodiments, a write manager circuit stores user data blocks in a write cache pending transfer to a non-volatile memory (NVM). The write manager circuit sets a write cache bit value in a forward map describing the NVM to a first value upon storage of the user data blocks in the write cache, and subsequently sets the write cache bit value to a second value upon transfer of the user data blocks to the NVM. A read manager circuit accesses the write cache bit value in response to a read command for the user data blocks. The read manager circuit searches the write cache for the user data blocks responsive to the first value, and retrieves the requested user data blocks from the NVM without searching the write cache responsive to the second value.

Buffer management in a data storage device wherein a bit indicating whether data is in cache is reset after updating forward table with physical address of non-volatile memory and jettisoning the data from the cache

A data storage system may have a number of data storage devices that each have a non-volatile memory connected to a memory buffer. The memory buffer can consist of a map unit having a predetermined size. In receipt of a data sector into the map unit of the memory buffer, the data sector may be identified as a runt with a runt module connected to the memory buffer and the non-volatile memory. The runt module can generate and subsequently execute a runt handling plan to fill the size of the map unit before storing the filled map unit in the non-volatile memory.

Runt handling data storage system

In one aspect a memory module storing a plurality of packets is provided. A self organizing heap contains elements associated with each of the packets. The self organizing heap reorders the packets based on packet passing rules. In another aspect, a plurality of elements associated with packets is provided. Each element includes a state machine. The state machine operates in accordance with packet passing rules. The state machine reorders the packets by selective swapping of adjacent elements.

Self organizing heap method includes a packet reordering method based on packet passing rules only reordering packets from a load/unload input signal is asserted

Included are embodiments for a method for servicing memory read requests. At least one embodiment of a method includes receiving read requests from the I/O device; testing predetermined fields from the read requests to predict a type of read request; and when the type of request is predicted to be a data read request, then route the read request to a first queue. Additionally, some embodiments include when the type of request is predicted to be a control read request, then route the read request to a second queue, wherein the second queue has a higher priority than the first queue; determining which of the first queue and second queue to read; retrieving at least one of the read requests from the determined queue; and processing the retrieved read request.

Servicing memory read requests

Included are embodiments for facilitating operation of an input/output (I/O) link. At least one embodiment of a method includes receiving a first cache line from a memory controller and determining whether the first cache line corresponds to a first portion of data. Some embodiments include, when the first cache line corresponds to the first portion of data, determining whether a second cache line is received and when the second cache line is not received, processing the first cache line. Similarly, some embodiments include when the first cache line does not correspond to the first portion of data, waiting for a cache line that does correspond to the first portion of data.

System and method for facilitating operation of an input/output link

Method and apparatus for allowing a direct memory access unit to have access to a virtual address space is accomplished by receiving a request for memory access from the direct memory access device; determining a device identifier according to the received request for memory access; determining a memory protection schema according to the determined device identifier; and granting the direct memory access unit access to memory in accordance with the determined memory protection schema.

Method and apparatus for direct input and output in a virtual machine environment containing a guest operating system

A method for allocating buffer capacity includes determining at least one characteristic of a first input/output (I/O) device that is coupled to a memory device interface, the memory device interface being configured to enable data transfers between the I/O device and a memory device, and buffering data corresponding to the first I/O device in a first portion of a buffer of the memory device interface, a size of the first portion being responsive to the at least one characteristic of the first I/O device.

Growing community of inventors

Ft. Collins, CO, United States of America

Matthew B Lovell