International Business Machines Corporation

Globalfoundries Inc.

Matthew B Baecher

Troy James Beukema

Lamiaa Msalka

Eugene R Atwood

James Stephen Mason

William Richard Kelly

Hayden C Cranford, Jr

John Francis Bulzacchelli

Todd Morgan Rasmus

Jeremy K Stephens

Minhan Chen

Charlie Chornglii Hwang

Huihao Xu

Mark R Taylor

Thomas J Bardsley

Joseph O Marsh

Stanislav Polonsky

Joseph Franklin Logan

Mounir Meghelli

Matthew James Paschal

John Farley Ewen

Pinping Sun

Gautam Gangasani

Trushil N Shah

Various embodiments of the present invention solve the problem of generating intermediate-time information useable to drive ZFE adaptation (for example, in connection with a digital receiver). Further, various embodiments of the present invention increase flexibility by enabling user-specified over-peaking and/or under-peaking (i.e. configurable equalizer tuning) with respect to a ZFE convergence (or lock) criterion.

System, method and software program for tuneable equalizer adaptation using sample interpolation

Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.

High data rate multilevel clock recovery system

Method and apparatus to calibrate sampling phases of a multi-phase sampling system. The method includes on-chip generating a pristine phase reference pattern signal for use in generating at least one reference output signal from a data path; sampling, responsive to a clock signal, the at least one reference output signal to obtain samples; and modifying a phase of the clock signal to align the obtained samples to pattern edges of at least one reference output signal. Both symmetric and asymmetric duty cycle distortion are removed from the pristine phase reference pattern signal input to the data path. The effects of asymmetric distortion in the data path output signal upon the phase calibration are cancelled by periodically inverting the at least one reference output signal. The method adjusts a first phase sampling clock signal output of an electronic phase rotator device to provide an initial alignment setting against a first edge of the reference output signal; and then implements phase calibration logic to align a second phase sampling clock signal against a second edge.

Calibration of sampling phase and aperature errors in multi-phase sampling systems

Apparatus, method and computer program product for determining presence and relative magnitudes of on-chip AC coupling capacitors in a high-speed differential receiver device. A BIST method is employed to ultimately produce a dock count proportional to the fall time of a capacitor, and in the case of differential capacitors a difference in count values. Each capacitor path has a controllable first DAC current or voltage source. A second DAC current or voltage source, later in the data path and isolated from the capacitor node(s), is controlled to offset the voltage contribution of the charged and discharging capacitor. A count is recorded, starting when a capacitor charging current is shut off, and ends (the count) when the voltage of the charged capacitor falls below a threshold. A difference in count between the two data path capacitors is calculated and reported. A state machine operates the sequencing and control of the BIST.

On-chip test for integrated AC coupling capacitors

Testing a Decision Feedback Equalizer ('DFE'), the DFE including a summing amplifier operatively coupled to a plurality of latches and an input signal line for receiving a data signal, including: preventing a differential data signal from being received by the summing amplifier; and iteratively for each tap to be tested: setting a tap coefficient for each tap to zero; setting an output of the plurality of latches to a predetermined value; setting a tap coefficient for the tap to be tested to a full scale value; and determining whether a resultant output signal from the DFE matches a predetermined expected output signal.

Testing a decision feedback equalizer ('DFE')

Testing a digital-to-analog converter (DAC), where the test is carried out iteratively for a plurality of digital test signal values, includes: providing the digital test signal to a DAC under test and to a servo; providing, by the DAC under test to a summer, an analog test signal, including converting the digital test signal to the analog test signal; providing, by the summer to an observation latch, a summed signal, including summing the analog test signal and an analog offset signal, the analog offset signal received from a second DAC; providing, by the observation latch to the servo, a sample of the summed signal; providing, by the servo to the second DAC in dependence upon the sample and the digital test signal, a digital offset signal, where the second DAC converts the digital offset signal to the analog offset signal; and storing, as a digital observation, the digital offset signal.

Testing a digital-to-analog converter

Digital testing of an analog driver circuit is enabled using a circuit including a control circuit for generating signals, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit, and a differential receiver circuit for converting the differential output signal to a single ended signal and transmitting the single ended signal. The testing includes skewing a differential output termination impedance, adjusting a differential receiver circuit voltage offset, selecting a differential driver circuit power level, enabling a decoder which activates only one differential driver circuit segment per test sequence, activating a segment, stimulating the differential driver circuit with digital test patterns, receiving differential driver circuit output, converting the output to a single-ended signal, and observing the single-ended signal.

System and method of digitally testing an analog driver circuit

A circuit of testing an analog driver circuit using digital scan-based test methodologies. The circuit of the present invention includes a control circuit for generating signals in response to a test enable signal, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal in response to the differential input signal and the signals generated by the control circuit, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit in response the signals generated by the control circuit, and a differential receiver circuit for receiving the differential output from the differential driver circuit, convert the differential output signal to a single ended signal and transmitting the single ended signal, all in response to the test enable signal.

System of digitally testing an analog driver circuit

An apparatus, method, microprocessor device and computer program for configuring a termination network of a communication device includes a voltage comparator for comparing a voltage across the termination network with a reference voltage; a logic arrangement for setting a digital control vector in response to a state returned by said voltage comparator; and a first switching apparatus for activating a first weighted-value resistor in response to the setting of the digital control vector. At least a second switching apparatus for activating a second weighted-value resistor, and wherein each of the first and the second weighted-value resistors is represented by a value in the digital control vector may be provided, the first and second resistors are connected in series or in parallel. The digital control vector may be stored in a logic register and distributed to a plurality of termination networks. The logic arrangement may include a finite state machine.

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Rock Tavern, NY, United States of America

Matthew B Baecher