Semiconductor Components Industries, LLC

On Semiconductor

Matthew Austin Tyler

Riley Beck

John J Naughton

Kent D Layton

Scott R Grange

David Willis

Justin Mark Gedge

Mark R Whitaker

A single wound single current transformer impedance measurement circuit for determining a circuit element parameter in a ground fault circuit interrupter circuit. The circuit includes a transconductance amplifier having first and second input terminals and first and second output terminals. In an embodiment, a first detector has input terminal coupled to the first output terminal of the transconductance amplifier and another input terminal coupled for receiving a first electrical signal. A second detector has a terminal coupled to the second output terminal of the transconductance amplifier and an input terminal coupled for receiving the first electrical signal. Alternatively, the second detector has an input terminal coupled to the first output terminal of the transconductance amplifier and another input terminal coupled for receiving the first electrical signal.

Single wound current transformer impedance measurement circuit

A method and circuit for determining a circuit element parameter in a ground fault circuit interrupter circuit. An electrical signal provided to a first node is used to generate another electrical signal at a second node. The electrical signal at the second node is multiplexed with a modulation signal to generate a modulated signal that is then filtered and converted into a digital representation of a portion of the circuit element parameter. The electrical signal at the second node is multiplexed with the modulation signal after it has been phase shifted to produce a modulated signal that is filter and converted into a digital representation of another portion of the circuit element parameter. In another aspect, a slope based solenoid self-test method is used for self-testing in a GFCI circuit. Alternatively, a method for determining a wiring fault is provided using a digital filter.

Impedance measuring circuit

A method for determining a circuit element parameter in a ground fault circuit interrupter circuit. An electrical signal provided to a first node is used to generate another electrical signal at a second node. The electrical signal at the second node is multiplexed with a modulation signal to generate a modulated signal that is then filtered and converted into a digital representation of a portion of the circuit element parameter. The electrical signal at the second node is multiplexed with the modulation signal after it has been phase shifted to produce a modulated signal that is filter and converted into a digital representation of another portion of the circuit element parameter. In another aspect, a slope based solenoid self-test method is used for self-testing in a GFCI circuit. Alternatively, a method for determining a wiring fault is provided using a digital filter.

Method for determining a circuit element parameter

Ground fault circuit interrupter and method

Current protection in integrated circuit having multiple pads. Different types of current protection structures may be associated with different pads. A common current discharge or charge path may be used to provide current to or draw current from various of these heterogenic current protection structures. Since a common current discharge or charge path is used, the metallization used to formulate a discharge solution is significant simplified. Additionally, the protection structures may be provided with selectively conductive regions that are approximately radially symmetrical around the circumference of the pad. Accordingly, if the protection structures are slightly off center with respect to the bond pad (due to, for example, mask alignment error), the error in the amount of active region around the circumference of the pad is at least partially averaged out.

Multi-pad shared current dissipation with heterogenic current protection structures

In one embodiment, an EEPROM device is formed to include a metal layer having an opening therethrough. The opening overlies a portion of a floating gate of the EEPROM device.

Method of forming an EEPROM device and structure therefor

A current protection circuit that uses a sequence of bipolar transistors to provide or draw current from a protected circuit node. An initial bipolar transistor has its emitter terminal coupled to the protected circuit node, with its collector terminal coupled to a current source or sink. One or more additional intermediary bipolar transistors are also provided in the sequence. Each additional intermediary bipolar transistor has its emitter terminal coupled to the base terminal of the previous bipolar transistor in the sequence, and has its collector terminal coupled to the current source or sink. To complete the sequence, a reverse-biased diode is coupled between the base terminal of the final intermediary bipolar transistor and the current source or sink. This allows for effective triggering of current protection for a protected circuit node without requiring a zener diode.

Current protection circuit using multiple sequenced bipolar transistors

A circuit that includes a controller and at least one control I/O pin. When the controller is placed into an initial state, the controller initializes the circuit into an initial operation mode. Depending on whether or not signal(s) satisfying predetermined criteria are applied to at least one of the control I/O pins, the controller will cause the circuit to enter one of two or more post-initial operation modes. Accordingly, by initializing the controller, and by controlling a signal on the control I/O pin(s), the operating mode of the circuit may be controlled. In one embodiment, a given control pin might be configurable to be both analog and digital, depending on the circuit's operation mode.

Initial decision-point circuit operation mode

A current dissipation circuit that dissipates excess current to or from a circuit node when that monitored circuit node experiences abnormal voltage conditions, rather than having that excess current being dissipated through other protected circuitry. The current dissipation circuit may use single well technology, and may even provide reverse voltage protection without necessarily triggering more significant current dissipation. In another embodiment, the current dissipation circuit is provided by a series connection of at least five alternating p-type and n-type regions provided between the monitored circuit node and a current source or sink.

Single well excess current dissipation circuit

An integrated high side switch with multi-fault protection. When a fault condition is detected, the switch is turned off. The switch includes a pair of transistors that are connected such that the source of the first transistor is connected with the source of the second transistor. The drain of the first transistor is thus connected to the supply voltage. A first current mirror generates a current sense output. A second current mirror generates an internal current to detect an over current fault condition. The transistors in the current mirrors are connected like the switch transistors. A high voltage operational amplifier and a transistor are used as feedback to insure that the voltage at the output of the current mirrors matches the voltage at the output of the switch. This ensures that the current mirrors generate scaled versions of the current flowing through the switch.

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Kaysville, UT, United States of America

Matthew Austin Tyler