Texas Instruments Corporation

Matthew A Woolsey

Marion C Lineberry

Gerard Chauvel

Yoshihide Iwata

Fred Jay Reuter

Judd E Heape

Basavaraj I Pawate

Douglas L Mahlum

Michael McMahon

Jihong Kim

A wireless data platform comprises a plurality of processors. Channels of communication are set up between processors such that they may communicate information as tasks are performed. A dynamic cross compiler executed on one processor compiles code into native processing code for another processor. A dynamic cross linker links the compiled code for other processor. Native code may also be downloaded to the platform through use of a JAVA Bean (or other language type) which encapsulates the native code. The JAVA Bean can be encrypted and digitally signed for security purposes.

Mobile electronic device having a host processor system capable of dynamically canging tasks performed by a coprocessor in the device

A computer system includes a main processing unit ( ) coupled to a DSP/memory module ( ). The DSP/memory module ( ) includes semiconductor memory ( ) and digital signal processor circuitry ( ) including one or more digital signal processors ( ). The DSP/memory module ( ) may be placed in standard main memory sockets, such as a SIMM or DIMM sockets, and used as conventional main memory. The memory module can also be used in a smart mode, wherein the digital signal processor ( ) performs operations on data for retrieval by the main processing unit ( ).

System signalling schemes for processor & memory module

A cache memory architecture,, which may be, for example, a set associative cache memory, has a cache controller (,) with an internal register for storing the address of the active line currently latched in the output buffer of the high speed cache data array (,) which stores the cached data values from the main memory. If a memory access request specifies an address which would be contained in the active line, the cache look-up mechanisms are disabled and the data is taken from the output buffer. The efficiency of the cache can be increased by linking a program to memory such that the number of cache lines used by one or more program loops are minimized.

Cache optimization for programming loops

A computer system includes a main processing unit (,) coupled to a DSP/memory module (,). The DSP/memory module (,) includes semiconductor memory (,) and digital signal processor circuitry (,) including one or more digital signal processors (,). The DSP/memory module (,) may be placed in standard main memory sockets, such as a SIMM or DIMM sockets, and used as conventional main memory. The memory module can also be used in a smart mode, wherein the digital signal processor (,) performs operations on data for retrieval by the main processing unit (,).

System signaling schemes for processor and memory module

A wireless data platform (10) comprises a plurality of processors (12,16). Channels of communication are set up between processors such that they may communicate information as tasks are performed. A dynamic cross compiler (80) executed on one processor compiles code into native processing code for another processor. A dynamic cross linker (82) links the compiled code for other processor. Native code may also be downloaded to the platform through use of a JAVA Bean (90) (or other language type) which encapsulates the native code. The JAVA Bean can be encrypted and digitally signed for security purposes.

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Plano, TX, United States of America

Matthew A Woolsey