Motorola Corporation

Freescale Semiconductor,inc.

Matthew A Thompson

Puneet Sharma

Willard E Conley

Bradley Paul Smith

Pawitter Jit Mangat

Whitson G Waldo, Iii

Kevin G Kemp

Percy V Gilbert

Subramoney V Iyer

Robert Elliott Boone

Pawitter Jit Singh Mangat

Rajive Dhar

An integrated circuit including a degradation monitoring circuit. The degradation monitoring circuit includes a comparison circuit having a delay element including an input coupled to a data node of a timing path and having an output to provide a delayed signal of a data signal of the data node. The comparison circuit includes a logic comparator that provides a logic comparison between a data signal of the data node and the output of the delay element. The monitoring circuit includes a sampling circuit that provides a sampled signal of the output of the logic comparator that is a sampled with respect to a clock signal of the clock signal line. The monitoring circuit includes a hold circuit that provides a signal indicative of a data signal of the data node transitioning within a predetermined time of an edge transition of a clock signal of the clock signal line.

Integrated circuit with degradation monitoring

A disclosed method for evaluating placement context sensitivity in the design of an integrated circuit includes accessing a standard cell library comprising a database of standard cells and determining generating boundary data for each of the standard cells. The boundary data for a standard cell indicates the layout of features located within boundary regions of the standard cell. The method includes merging or consolidating boundary data for any two standard cells if their boundary data is the same to determine a canonical or minimal set of boundary regions. The disclosed method further includes enumerating and evaluating all combinations of pairs of the canonical boundary regions and, responsive to identifying of a proximity-based sensitivity or exception, modifying, notating, or otherwise remediating the applicable one or more standard cells that correspond to the boundary region combination that raised the exception.

Method for analyzing placement context sensitivity of standard cells

A method of forming a semiconductor device by obtaining a substrate, with a first surface and a second surface, where the substrate has a first material and a second material separated by an etch stop. A membrane film is deposited on the first surface of the substrate and the substrate is patterned to form an opening through the second surface and through the second material to the etch stop layer. The etch stop layer and the first material in the opening are then patterned to form the semiconductor device. This method may be used to form a lithographic mask and further embodiments of the present invention.

Method of forming mask with angled struts of reduced height

A mask (300) for scattering angular limited projection electron beam lithography, including a substrate (102) having an opening (103) extending into the substrate, a membrane layer (204) extending over the substrate, the membrane layer including a window portion (209) that overlies an opening in the substrate and being formed of a material having a first electron scattering power, a patterned scattering layer overlying the membrane layer, at least along the window portion of the membrane layer, the patterned scattering layer being formed of a material having a second electron scattering power that is greater than the first electron scattering power, and an encapsulating layer (210) overlying the patterned scattering layer, the encapsulating layer having a third electron scattering power that is less than the second electron scattering power.

Method of forming a semiconductor device utilizing scalpel mask, and

A pattern of dummy structures (20) is added to the layout pattern of an integrated circuit (10) to equilibrate the polishing rate across the surface of a semiconductor substrate (11). The location of each dummy structure (20) is predetermined so that it does not intersect a well boundary (17) or an active region (21,27), and does not fall under a conductive material such as a layer of polysilicon (22,28) or an interconnect structure (23,29).

Integrated circuit having a dummy structure and method of making

A method of patterning an X-ray master mask (21) is described by using reduction projection. An X-ray mask (21) is provided with a photoactive material coating a plating base layer (24). The X-ray mask (21) is positioned under the reduction projection tool. The photoactive material on the X-ray mask (21) is exposed from a pattern (13) in the reduction projection tool.

Growing community of inventors

Round Rock, TX, United States of America

Matthew A Thompson