Photon Vision Systems, Inc.

Silicon Video, Inc.

Matthew A Pace

Jeffrey Jon Zarnowski

Michael Joyner

Thomas Vogelsong

Robert Iodice

Jeffrey J Zamowski

A bus system which includes two or more voltage-to-current transformers, a common bus, a terminal bus coupled to a voltage source, two or more first switches, and a selection circuit. Each of the voltage-to-current transformers converts a voltage signal to a current signal. The common bus carries the current signals from the voltage-to-current transformers to an output bus. Each of the first switches has a first position where an output from one of the voltage-to-current transformers is coupled to the common bus and a second position where the output is coupled to the terminal bus. The selection circuit is coupled to each of the first switches and controls movement of each of the first switches between the first and second positions.

Current mode analog signal multiplexing bus and a method thereof

A bus system and an imager for transferring signals from a plurality of signal streams to an output includes a plurality of signal buses in parallel and a control system. The control system multiplexes the signals from two or more of the plurality of signal streams onto two or more of the plurality of signal buses and allows the signals to substantially charge each of the two or more of the plurality of signal buses before demultiplexing the signals to the output. A method for transferring signals includes multiplexing signals on to two or more of a plurality of signal buses and allowing the signals to substantially charge each of the two or more of the plurality of signal buses before demultiplexing the signals to an output.

Video bus for high speed multi-resolution imagers and method thereof

An analog video bus architecture that utilizes the column parallel nature of CMOS imagers and more specifically Active Column Sensors, that eliminates the need for multi-port imagers, by increasing the useable bandwidth of single port imagers. An adaptation of this invention allows for either binning or interpolation of pixel information for increased or decreased resolution along the columns and more specifically for ACS imagers binning or interpolation along the rows. In this bus, the single video bus is replaced by multiple video buses and instead of selecting only one column for reading multiple columns are also pre-selected in-order to pre-charge the video bus. The video buses are then de-multiplexed back on to one port at the desired element rate. This architecture utilizes the column oriented video bus of CMOS imagers. It divides the large video bus capacitance by the number of video buses used. In addition, it allows multiple pixel time constants to precharge the video bus. The best commercially available imager designs now claim 40 MHz per analog port and suffer from reduced signal to noise ratios. To overcome this fundamental bandwidth limitation, imager designs in the past have had to increase the number of video ports per imager to achieve high frame rates. Multiple ports per imager breaks the focal plane into segments that are typically reassembled via post processing in a host computer. The other problem with multiple ports is each segment of the imager will have its own offsets and resultant Fixed Pattern Noise (FPN). PVS-Bus&trade; eliminates the objectionable segmentation and simplifies high-speed system design. Also, by utilizing the column parallel nature of CMOS video buses a method and improved method of using the PVS-Bus of binning and interpolation is described which results in increased frame rate, and for decreased or increased resolution.

Video bus for high speed multi-resolution imagers

A new method of forming a photogate structure called a &ldquo;Charge Snare Device&rdquo; (CSD) uses only a single layer of polysilicon where prior art methods used two or more layers for constructing the gate nodes. Typical CCD structures utilize three layers of polysilicon and CID structures utilize two layers of polysilicon and neither of the prior art structures are suitable for standard sub micron processes. The new CSD device allows biasing of the photogate to the full potential that the process will allow for greater full well for a given pixel size and therefore an improved signal to noise ratio. Charge transfer between the collection site and the sense site isn't controlled as in all previous devices, rather the collection site is completely enclosed by the sense site, effectively snaring all collected photon generated charge as it diffuses and drifts to the sense site. The new photogate structure is suitable for passive pixels, Active Pixel Sensors (APS) or Active Column Sensors (ACS).

Single polysilicon CMOS pixel with extended dynamic range

An improved low voltage, small surface area, high signal-to-noise ratio photo gate includes a layer of photoreceptive semiconductor material having an impurity concentration selected to enhance the formation of hole electron pairs in response to photons impinging on a surface of the substrate, an electrode extending from the surface of the substrate into the substrate a substantial distance; an insulating layer disposed between the electrode and the substrate for electrically insulating the electrode from the substrate; so that upon the application of an electrical potential to the electrode, a potential well is formed in the substrate surrounding the electrode for accumulating charge generated when photons impinge on the surface of the substrate surrounding the electrode.

Photo receptor with reduced noise

A CMOS imager includes a photosensitive device such as a photosensitive device such as a photodiode or photogate having a sense node coupled to an FET located adjacent to the photosensitive region. Another FET, forming a differential input pair of an operational amplifier is located outside of the array of pixels. The operational amplifier is configured for unity gain and a row or column of input FETs is connected in parallel. A correlated double sampler is connected to the output of the operational amplifier for providing a fixed pattern noise free signal.

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Cortland, NY, United States of America

Matthew A Pace