International Business Machines Corporation

Matthew A Krygowski

Steven G Glassen

Moon Ju Kim

Allen H Preston

David E Stucki

Arthur J Sutton

Robert S Capowski

William Wu Shen

Benedicto U Messina

Jonel George

Brian William Curran

Thomas M Brey

Tin-Chee Lo

Michael Ignatowski

Lishing Liu

Gregory Salyer

Trinh Huy Nguyen

Sanjay Bhikhubhai Patel

Donald W Price

Patrick M Gannon

Neal T Christensen

Yee-Ming Ting

Bruce L McGilvray

Ronald F Hill

Terrence K Zimmerman

Frederick J Cox

William D Silkman

Thomas O Curlee, Iii

William K Rodiger

Frank P Cartman

George L Chiesa

Theodore A Papanastasiou

Michael P Witt

Sandy N Luu

A data processing system has a processing unit and a memory which provides a common pool of physical storage. This storage is initially assigned as either main storage or expanded storage during power on. Subsequent to the initial assignment, storage assigned as main storage or expanded storage may be unassigned and thus returned to the common pool. Once returned to the common pool, the storage may be reassigned as either main storage or expanded storage. The storage reassignment is done dynamically without requiring a reset action and transparent to the operating system and any active application programs.

Main storage and expanded storage reassignment facility

In a partitioned process environment, storage is reassigned by a shuffle of guest absolute address spaces which may be reassigned among partitions without restriction as to the position of the space to be reassigned relative to the position of the partition to which it is to be assigned. The reassignment is accomplished by adjusting the origin addresses by an adjustment value corresponding to the size of the address space of an additional memory area to be added to a selected partition. Furthermore, the size of the address space of the selected partition is increased by the same adjustment value. The system employs duplicated origin and limit arrays which are used to convert from a partition (guest) absolute address to a system (host) absolute address and uses duplicated configuration arrays by which the system absolute addresses are converted to physical memory addresses. Revised origin and limit information and configuration information is stored in an origin and limit array in the stand by state and in a configuration array in the stand by state. Autonomously operating circuitry is responsive to control signals to temporarily suspend memory commands from the input-output system, to reconfigure the origin and limit arrays and the configuration arrays to enable the system to use the revised information and, thereafter, to resume the processing of memory commands from the input-output system.

Method and apparatus for dynamic storage reconfiguration in a

Dynamic Reconfiguration of main storage and expanded storage by means of

A method and device for correcting hardware errors without loss of resources while maintaining continuous operation of the computer system. Same method and device can be used for repair or addition of hardware parts to this system. The method and device can operate in a fault tolerant system which allows continuous service during the occurrence of a hardware failure or while parts are being repaired or added to the system. The method and device also use Hamming code to detect and correct all hardware failures, particularly a soft-soft uncorrectable error and a special uncorrectable error or a SUE.

Memory and system for recovery/restoration of data using a memory

Fault tolerant systems allow continuous service during the occurrence of a hardware failure. To provide such service, usually dual copies of data are stored in case of a hardware failure affecting the original copy. This dual copying causes the system an overall performance degradation. The present invention discloses a device and method for performing parallel fetch and store commands, allowing multiple copying of data into storage without affecting the performance of the system. In one embodiment of the invention, a method is described utilizing a multiprocessor system having two system controllers (SCs) and a plurality of requestors defined as a plurality of central processors (CPs) and input-output (I/O) processors. Asymmetric structure is accomodated. Single and dual requests can be intermixed. Each requestor has access to both system controllers, allowing either controller to process a requestor issued command. An interlocking data protection mechanism is also provided to protect data integrity by allowing requestors data access to a given unit of data only on a one at a time basis. Data exclusivity ownership access to a given unit of data is being provided by and removed by the system controllers. When a command is issued by one of the requestors, the system controllers process the command and provide the requestor with a response upon processing completion. In the mean time, the requestor can perform any required data updates. This concurrent processing improves the performance of the system but also protects its integrity.

Device and method for fault tolerant dual fetch and store

A memory access system for improving memory access when addressing dynamic random access modules (DRAMs). The memory access system includes a main memory and a memory controller. To improve memory access, both the memory controller and the main memory hardware remember the row address of the last access. Macro operation commands for fetch and store contain the last row address. The main memory hardware redrives that row address to the DRAMs after completion of an access, so that the memory controller need not provide a row address to the memory for each command of a command sequence.

Memory access system including a memory controller with memory redrive

A method of automatically invoking a recoverable and fault tolerant implementation of the complemented/recomplemented (C/R) error correction method without the assistance of a service processor when an excessive error is detected in main storage (MS) by ECC logic circuits. An excessive error is not correctable by the ECC. These novel changes to the C/R method increase its effectiveness and protect the C/R hardware against random failure. Further, if an excessive error is corrected in a page in MS, an excessive error reporting process is provided for controlling the reporting using a storage map to determine if a previous correction in that page has been reported. If it has been reported, then no further reporting of soft excessive errors is made for that page. A service processor is signaled in parallel to update its persistent copy of the storage map so that on a next initializations of MS the memory map can be restored in the memory. The memory map is used to assist the repair of failing parts of MS, and is reset after MS is repaired.

Excessive error correction control

A coherence directory and its methods of operation are disclosed for private processor caches in a multiple processor system to control data coherence in the system. It provides cross-invalidate (XI) controls for the assignment of exclusive and public ownership to data units in the processor caches, including required cross-invalidation of data units among the processor caches to obtain data coherence in the system in an efficient manner. The coherence directory can be used in a multiple processor system with or without any shared second level (L2) cache, shared or private. When a shared L2 cache is used to improve system access time, the coherence directory can also be used as the second level directory for the shared L2 cache and eliminate the need for any additional L2 directory(s).

Coherence control by data invalidation in selected processor caches

A fast path (comprising control and data busses) directly connects between a storage element in a storage hierarchy and a requestor. The fast path (FP) is in parallel with the bus path normally provided through the storage hierarchy between the requestor and the storage element controller. The fast path may bypass intermediate levels in the storage hierarchy. The fast path is used at least for fetch requests from the requestor, since fetch requests have been found to comprise the majority of all storage access requests. System efficiency is significantly increased by using at least one fast path in a system to decrease the peak loads on the normal path. A requestor using the fast path makes each fetch request simultaneously to the fast path and to the normal path in a system controller element (SCE). The request through the fast path gets to the storage element before the same request through the SCE, but may be ignored by the storage element if it is busy. If accepted, the storage element can start its accessing controls sooner for a fast path request, than if the request is received from the normal path. Every request must use SCE controlled cross-interrogate (XI) and storage protect (SP) resources. Fast path request operation requires unique coordination among the XI and SP controls, the SCE priority controls, and by the storage element priority controls. When the accessed data is ready to be sent by the storage element, it can be sent to the requestor faster on the fast path data bus than on the SCE data bus. The fast path data bus may be used to transfer data for requests ignored from the fast path.

Direct parallel path for storage accesses unloading common system path

The disclosure provides a plurality of embodiments for controlling the bus paths for a line of data from any cache in a multiprocessing system (MP) to any requesting cache or I/O channel processor in the MP. The data transfers can occur in parallel among plural CPU caches, channel processors and main storage (MS) sections using crosspoint switches in a manner which utilizes the high circuit count of LSI modules without substantially utilizing the module I/O pin count to enable MP structures to contain more CPUs than could be contained with conventional bussing.

System for independent cache-to-cache transfer

Storage access requests are forwarded from plural input/output channels to shared main storage. An address word in each request designates the identity of the source channel (CHID) and 'destination' address (of a doubleword space in storage relative to which one, two or four 'data' words shall be transferred). EOT tag signal provides demarcation of requests and also uniquely identifies '1-wide' input (Store) requests. Quadword (QW) tag, presented with '4-wide' requests, enables the storage access system to use a single address in the request to locate two contiguous doubleword spaces in storage. Data tags (D1, D2), presented on a selective basis enable the access system to selectively steer (reorder the positions of) data words in an input request relative to word halves of the addressed space. Consequently the data repositioning function associated with Read Backward operations does not require reordering of data words in the channel buffers (saving handling time and expense of 'steering' circuits in the individual channels). In association with a '1-wide' input request a single data tag, D1 or D2, is used to steer the single data word of the request into either half of the addressed space on a selective basis.

Request forwarding system

This adapter operates in time division multiplex mode between an input/output channel processing subsystem and a storage access subsystem of a data processing system. The adapter is capable of sustaining multiple processes of information transfer concurrently relative to both subsystems. It is also capable of concurrently sustaining ancillary processes for verifying and timing out individual transactions of the information transfer processes.

Channel storage adapter

Growing community of inventors

Hopewell Junction, NY, United States of America

Matthew A Krygowski