International Business Machines Corporation

Matthew A Cooke

Michael Stephen Floyd

Brian Thomas Vanderpool

Jeffrey A Stuecheli

Gerald Mark Grabowski

Su Liu

Kai Liu

Gregory Scott Still

Daniel Lawrence Stasiak

Manjunath Ravi

Zhichao Li

Hassan Naser

Dongkook Park

Calist Friedman

Juan Medina

Embodiments relate to a system and method for managing energy consumption of one or more processor cores in a multicore processing device. The method includes establishing a temporal interval that includes a plurality of temporal periods and an interval energy target for one or more processor cores. The method also includes determining for each temporal period a period energy target for the processor cores and determining a processor core throttling state for the processor cores. The method further includes adjusting the respective period energy target and the respective processor core throttling state at the beginning of each successive temporal period. The method also includes converging, subject to the adjusting, as each respective temporal period of the plurality of temporal periods is concluded, a total period energy consumption of the processor cores with the interval energy target.

Proxy-based instruction throttling control

A system and method for managing energy consumption of one or more processor cores in a multicore processing device. The method includes translating each activity level of the one or more processor cores to a respective charge value. The method also includes generating, at least partially subject to each translated charge value, one or more charge replenishment requests associated with the one or more processor cores. The method further includes transmitting the one or more charge replenishment requests to a pending queue prior to a delay queue.

Current prediction-based instruction throttling control

A system and method for managing energy consumption of one or more processor cores in a multicore processing device. The method includes recording an activity level of one or more processor cores within a multicore processing device and translating each activity level of the one or more processor cores to a respective charge value. The method also includes generating, at least partially subject to each translated charge value, one or more charge replenishment requests associated with the one or more processor cores. The method further includes determining the one or more charge replenishment requests exceeds a power delivery capacity to the multicore processing device. The method also includes regulating the processing activity of the one or more processor cores to decrease a power consumption for the one or more processing cores.

A technique for dynamically adjusting a configuration of a computing system includes determining, during execution of a workload on the computing system, one or more characteristics of the workload. A system configuration from a plurality of system configurations available for the computing system is selected based on the one or more characteristics of the workload. A current configuration of the computing system is adjusted according to the selected system configuration, during the execution of the workload.

Workload-based cognitive dynamic computing system optimization

An approach to creating a semiconductor chip including a semiconductor substrate with one or more topside metal layers and one or more backside metal layers. The approach creates the semiconductor chip with one or more semiconductor devices with wiring interconnects in the one or more topside metal layers on the semiconductor substrate and one or more inductors in the one or more backside metal layer. Furthermore, the approach creates the semiconductor chip with one or more through silicon vias extending through the semiconductor substrate connecting the one or more inductors in the one or more backside metal layers and the one or more semiconductor devices with wiring interconnects in the one or more topside metal layers on the semiconductor substrate.

Semiconductor device with backside inductor using through silicon vias

A method for predicting post-placement timing-analysis results includes obtaining, for a logic design, logic-synthesis data and logic-planning data. The method also includes inputting, into a neural network, the logic-synthesis data and logic-planning data. The neural network is trained to correlate logic-synthesis data and logic-planning data with post-placement timing-analysis results. The method also includes receiving, from the neural network, predicted post-placement timing-analysis results.

Growing community of inventors

Cedar Park, TX, United States of America

Matthew A Cooke