Qualcomm Incorporated

Mattheus Heddes

Robert Hardacker

Nhon Toai Quach

Rahul Gulati

Mainak Biswas

Jeffrey Shabel

Pranjal Bhuyan

Systems and methods are disclosed for error correction control (ECC) for a memory device comprising a data portion and an ECC portion, the memory device coupled to a system on a chip (SoC). The SoC includes an ECC cache. On receipt of a request to write a line of data to the memory, a determination is made if the data is compressible. If so, the data line is compressed. ECC bits are generated for the compressed or uncompressed data line. A determination is made if an ECC cache line is associated with the received data line. If the data line is compressible, the ECC bits are appended to the compressed data line and the appended data line is stored in the data portion of the memory. Otherwise, the ECC bits are stored in the ECC cache and the data line is stored in the data portion of the memory.

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Raleigh, NC, United States of America

Mattheus Heddes