Stmicroelectronics S.r.l.

Sgs-thomas Microelectronics S.r.l.

Sgs-italy Microelectronics S.r.l.

Matteo Zammattio

Rino Micheloni

Giovanni Campardo

Carla Maria Golla

Stefano Zanardi

Andrea Ghilardelli

Marco MacCarrone

Jacopo Mulatti

Stefano Ghezzi

Stefano Commodaro

Ilaria Motta

Marcello Carrera

Donato Ferrario

The memory device has hierarchical sector decoding. A plurality of groups of supply lines is provided, one for each sector row, extending parallel to the sector rows. A plurality of switching stages are each connected between a respective sector and a respective group of supply lines; the switching stages connected to sectors arranged on a same column are controlled by same control signals supplied on control lines extending parallel to the columns of sectors. For biasing the sectors, modification voltages are sent to at least one selected group of biasing lines, and control signals are sent to the switching stages connected to a selected sector column.

Nonvolatile memory device with hierarchical sector decoding

A voltage boost device includes a first boost stage and a second boost stage connected to an input terminal and to an output terminal, the output terminal supplying an output voltage higher than a supply voltage. The input terminal receives an operating condition signal having a first logic level representative of a standby operating state and a second logic level representative of an active operation state. The first boost stage is enabled in presence of the second logic level of the operating condition signal, and is disabled in presence of the first logic level of the operating condition signal; the second boost stage is controlled in a first operating condition in presence of the first logic level of the operating condition signal, and is controlled in a second operating condition in presence of the second logic level of the operating condition signal.

Low consumption voltage boost device

A temperature-related voltage generating circuit has an input terminal receiving a control voltage independent of temperature, and an output terminal delivering a temperature-related control voltage. The input and output terminals are connected together through at least an amplifier stage adapted to set an output reference voltage from a comparison of input voltages. The voltage generating circuit also includes a generator element generating a varying voltage with temperature and connected between a ground voltage reference and a non-inverting input terminal of the amplifier stage. The amplifier stage has an output terminal adapted to deliver a multiple of the varying voltage with temperature to an inverting input terminal of a comparator stage. The comparator stage has its output connected to the temperature-related voltage generating circuit and a non-inverting input terminal receiving the control voltage independent of temperature to evaluate the difference between the control voltage independent of temperature and said voltage being a multiple of the varying voltage with temperature and to output a temperature-related control voltage having at room temperature a mean value which is independent of its thermal differential and increases with temperature. The voltage generating circuit can be incorporated into a regulator for a drain voltage of a single-supply memory cell.

Memory cell voltage regulator with temperature correlated voltage generator circuit

The invention relates to a method and a circuit for regulating a pulse synchronization signal (ATD) for the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells, so as to also generate an equalization signal (SAEQ) to a sense amplifier. The SAEQ pulse is blocked (STOP) upon the row voltage reaching a predetermined sufficient value to provide reliable reading. Advantageously, the pulse blocking is produced by a logic signal (STOP) activated upon a predetermined voltage value being exceeded during the overboost phase of the addressed memory row.

Method and circuit for regulating the length of an ATD pulse signal

Switching circuit comprising a reference voltage, an input voltage, suitable to assume alternatively a negative value or a value equal to said reference voltage, an output node, suitable to assume selectively three possible voltage values equal to a supply voltage, to the reference voltage, to the input voltage or, alternatively, to be kept floating, in response to a first, a second, a third, a fourth, a fifth, a sixth control logic signal, switching between the supply voltage and the reference voltage.

Switching circuit with an output voltage changing among four possible

A method and a circuit generate a pulse synchronization signal (ATD) for timing the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells. The method consists of duplicating the ATD signal into at least one pair of signals and propagating such signals through separate parallel timing chains at the ends of which the ATD signal is reinstated, the chains being alternately active.

Method and circuit for generating an ATD signal to regulate the access

A switching circuit comprising a supply voltage, a reference voltage, a line suitable to carry a negative voltage, an input for a control signal, suitable to supply to a first output node and to a second output node two voltages respectively equal to supply voltage and to line voltage or, alternatively, to line voltage and to supply voltage, in response to the control signal. There are first interrupting means, second interrupting means, third interrupting means, fourth interrupting means, the first and third interrupting means connected in series between the supply voltage and the line, the second and fourth interrupting means connected in series with each other and in parallel to first and third interrupting means, the first output node corresponding to common node between the first interrupting means and the third interrupting means, the second output node corresponding to common node between the second interrupting means and the fourth interrupting means, the control signal controlling first interrupting means and second interrupting means in such a way that when the first interrupting means are open, also the fourth interrupting means are open whereas the second interrupting means and third interrupting means are closed, connecting the first output node to line and the second output node to supply voltage, and vice versa when the first interrupting means are closed, also fourth interrupting means are closed whereas the second interrupting means and third interrupting means are open, connecting the first output node to supply voltage and the second output node to line.

Switching circuit

A band-gap reference voltage generator comprises an operational amplifier comprising a first input and a second input, the first input being coupled to a first feedback network and the second input being coupled to a second feedback network both coupled to an output of the operational amplifier providing a reference voltage. The first feedback network contains an emitter-base junction of first bipolar junction transistor and the second feedback network contains an emitter-base junction of second bipolar junction transistor. A selectively activated current supply supplies a bias current to the operational amplifier, the current supply being deactivatable in a substantially zero power consumption operating condition for turning the reference voltage generator off. A start-up circuit activated upon start-up of the reference voltage generator for a fixed, prescribed time interval forces a start-up current to flow through the first bipolar junction transistor means.

Band-gap reference voltage generator

An integrated device having an N-type well region formed in a P-type substrate and an N.sup.+ type contact ring housed in the well region. The well region forms respective capacitors with a conductive layer superimposed on the substrate, and with the substrate itself. The conductive layer and the substrate are grounded, and the contact ring is connected to the supply, so that the two capacitors are in parallel to each other and, together with the internal resistance of the well region, form a filter for stabilizing the supply voltage. When connected to an input buffer stage of the device, the filter provides for damping the peaks produced on the supply line of the input buffer by high-current switching of the output buffers.

Integrated device with pads

An address transition detection circuit having a number of cells supplied with respective address signals and outputs connected in a wired NOR configuration to generate a pulse signal on detecting transitions of their respective address signals. The pulse signal is supplied to a source stage for generating an address transition signal having a first and second switching edge on receiving the pulse signal. The source stage has a monostable stage for generating an end-of-transition signal with a predetermined delay following reception of the pulse signal; and an output stage connected to the cells and to the monostable stage, which generates the first switching edge of the address transition signal on receiving the pulse signal, and the second switching edge on receiving the end-of-transition signal. The monostable stage presents a compensating structure for maintaining the delay in the switching of the end-of-transition signal despite variations in temperature and supply voltage.

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Milan, Italy

Matteo Zammattio