Conexant Systems, Inc.

Glonav Limited

Avago Technologies International Sales Pte. Limited

St-ericsson Sa

Broadcom Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Matteo Conta

Seema Butala Anand

Akbar Ali

Andrea Baschirotto

Woogeun Rhee

Stefano D'Amico

Valentina Della Torre

Howard Chi

Ramesh Chokkalingam

Lorenzo Crespi

Larry Baoqi Li

David A Weldon

Ramesh Chokkalingham

The present disclosure is directed to a dual output path LNA that can be used to break the tradeoff between the output impedance and linearity of an LNA without the problems of a programmable output impedance LNA. In an embodiment, the dual output path architecture includes an LNA driving a low level of impedance in a low voltage gain path, thus achieving high linearity in the presence of large blockers, and driving a high level of impedance in a high voltage gain path to increase the LNA's voltage gain and minimize performance degradation due to a noisier, low power receiver front-end chain following the LNA. The present disclosure is further directed to a local oscillator (LO) offset circuit with low power and reduced spur generation.

Low power spectrally pure offset local oscillator system

Single input, dual output path low-noise amplifier

A transceiver or RF front end employing a transformer with a low loss transmit/receive (T/R) switch circuit in the ground path. In various embodiments, differential outputs of a power amplifier are coupled to the first winding of the transformer, while the input of a low noise amplifier is coupled to the second side of the transformer via a matching inductor. The T/R switch circuit, which may be a thin oxide CMOS transistor, is coupled between the second side of the transformer and ground. In operation, the T/R switch circuit may be enabled during transmit mode operations of the power amplifier, such that a low impedance path to ground is provided at the input of the low noise amplifier, thereby protecting it from high voltage swings generated by the power amplifier.

Transceiver front end with low loss T/R switch

A capacitive voltage converter comprising a switched capacitor array having a voltage input and a voltage output. A skip gating control coupled to the switched capacitor array and configured to control a switching activity of the switched capacitor array. A resistance look-up table coupled to the switched capacitor array and configured to control a resistance value of the switched capacitor array.

System and method for capacitive DC-DC converter with variable input and output voltages

There is described a continuous time filter of at least a second (or higher) order, comprising one or more first order filter stages of a first type, the or each first order filter stage of the first type comprising a reactive component and an impedance dependent on the difference between the input and output voltages of the filter stage. The filter includes at least one first order filter stage of a second type, the or each second order filter of the second type comprising a reactive component and an impedance dependent on the sum of the input and output voltages of the filter stage. The filter includes a transfer function of the continuous time filter that is obtained comprising complex poles.

High order continuous time filter

In an integrated circuit having a number of circuit units on a single semiconductor chip, particularly in a system-on-chip integrated circuit including an integrated transceiver, interference between the circuit units is suppressed using on-chip resonant elements. Each resonant element has at least one on-chip capacitor and at least one on-chip conductive line constituting an inductance. The capacitance-inductance combinations are arranged to be resonant at one or more frequencies at which radio frequency energy is generated by the circuit units. The capacitive part of each series resonant combination is formed as a plurality of capacitor elements forming in an array to minimise self-inductance. Also disclosed is a filtering arrangement in which each circuit unit is individually supplied from the tap of a series resistive-capacitance combination to provide low-pass filtering. The resistance of such a combination may be configured as an FET to allow the circuit unit to be individually powered down to a low leakage state.

Radio frequency noise and interference suppression in an integrated circuit

The present invention addresses a need for reducing the power consumption in a baseband filter used in a front-end wireless receiver while providing the necessary linearity. In particular, relatively high linearity can be obtained with lower power consumption than has heretofore been the case. This is achieved in embodiments of the invention using an optimized single-branch fully differential structure which operates as a 'composite' source-follower (when using CMOS devices) with an ideal unitary dc gain. A positive feedback internal to the source follower allows one to synthesize two complex-poles.

Filter circuit

An electric circuit, for use in a phase lock loop circuit, the electric circuit comprising: a first circuit element, being a phase frequency detector or a charge pump; at least one LC resonant loop, the first circuit element forming part of the loop; and means arranged to reduce ringing in said at least one LC resonant loop.

Electronic circuit

A low-power quadrature generator is provided for accurately generating in-phase signals and quadrature signals.

Quadrature VCO system and method

RF voltage amplifier circuits which have high voltage amplifier gain and input signal frequency range, and a method for boosting the voltage amplifier gain and input signal frequency range in such circuits is provided. A method includes the steps of providing a voltage amplifier having a transistor with the grounded source and the drain connected to a power supply via a resistive load, and providing an integrated inductor for biasing the transistor, having an inductor connecting an input signal terminal to the gate of the transistor and a capacitor connecting the gate and the source of the transistor. The next step includes selecting a resonant frequency of the integrated inductor at a frequency where the voltage amplifier gain is starting to roll-off, for boosting the voltage amplifier gain and the input signal frequency range. The integrated inductor preferably operates at a resonant frequency approximately matching the roll-off frequency of the voltage amplifier. In another embodiment the voltage amplifier has a common emitter (CE) gain stage, a common base (CB) cascade stage directly-coupled to the CE gain stage, and a constant current mirror source. The integrated inductor has two inductors, each connected to one input of the amplifier input signal pair and a capacitor connecting the inductors. This circuit can be adapted for fully differential operation mode or for single ended operation mode.

Fully integrated broadband RF voltage amplifier with enhanced voltage gain and method

In a phase lock loop, a charge pump includes a current mirror circuit. The current mirror circuit contains a bias current source and a current mirror source which mirrors the current of the bias current source. The current mirror source is turned on and off in accordance with an output signal from a phase detector to produce correction signals for a VCO. To conserve power, circuits are provided for turning the bias current source on just before it is needed by the current mirror source and for turning the bias current source off just after the current mirror source turns off.

Low noise low power charge pump system for phase lock loop

A phase-locked loop includes a phase/frequency detector, a charge pump, a loop filter, an oscillator and a feedback circuit coupled between the oscillator and the phase/frequency detector. The loop filter includes a first temperature-variable well resistor and has a gain directly related to resistance of the first resistor. An oscillator coupled to the loop filter includes a voltage-to-current converter that generates a reference current based on the loop filter voltage, and a current-controlled oscillator that generates the output clock based on the value of the reference current. The voltage-to-current converter includes a first transistor that receives the loop filter voltage at a gate and a second temperature-variable well resistor coupled to the source of the first transistor. The oscillator gain is indirectly related to the resistance of the second resistor. The second well resistor and first well resistor have substantially equal resistances and substantially equal temperature coefficients. Since the loop bandwidth includes the product of the loop filter gain and oscillator gain, the effect of temperature-induced resistance variations on loop bandwidth is minimized.

Phase-locked loop having temperature-compensated bandwidth control

A gated-delay locked loop that generates an output clock in phase with and having a frequency which is an integer multiple of the frequency of a reference clock. The gated delay-locked loop includes a voltage-controlled gated oscillator having first and second serially connected voltage-controlled delay elements that each introduce a time delay to produce a first delayed clock and the output clock. An S-R flip-flop receives the first delayed clock on its R-input and either the output clock or the reference clock on its S-input to produce a loop clock. The loop clock is provided to the first delay element. A multiplexer selects the reference clock as the S input to the flip-flop once every N cycles, and selects the output clock as the S input the remaining N&minus;1 cycles. A phase detector, a charge pump and a loop filter compare the phase of the output clock to the phase of the reference clock and apply a voltage to the delay elements to correct any phase differences.

Gated delay-locked loop for clock generation applications

A source-switched or gate-switched charge pump having a cascoded output. A first current-mirror comprised of p-channel CMOS transistors is coupled on one side of an output node and a second current mirror comprised of n-channel CMOS transistors is coupled on the opposite side of the output node. A reference current source is coupled between the current mirrors. A p-channel CMOS cascode transistor is coupled between the first current mirror and the output node, and an n-channel CMOS cascode transistor is coupled between the second current mirror and the output node. A p-channel CMOS transistor switch is coupled to either the source or the gate of the output transistor of the first current mirror and receives a first control signal at its gate. An n-channel CMOS transistor switch is coupled to either the source or the gate of the output transistor of the second current mirror and receives a second control signal at its gate.

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Irvine, CA, United States of America

Matteo Conta