Intel Corporation

Micron Technology Incorporated

Mattan Erez

Ronny Ronen

Adi Yoaz

Stephan Jourdan

Lihu Rappoport

Bob Valentine

Stephan J Jourdan

Gregory Pribush

Freddy Gabby

Methods and apparatus for restoring a meta predictor system upon detecting a branch or binary misprediction, are disclosed. An example apparatus may include a base misprediction history register to store a set of misprediction history values each indicating whether a previous branch prediction taken by a previous branch instruction was predicted correctly or incorrectly. The apparatus may comprise a meta predictor to detect a branch misprediction of a current branch prediction based at least in part on an output of the base misprediction history register. The meta predictor may restore the base misprediction history register based on the detecting of the branch misprediction. Additional apparatus, systems, and methods are disclosed.

Meta predictor restoration upon detecting misprediction

A branch predicting apparatus is disclosed that reduces branch mispredictions in a processor. The branch prediction apparatus includes a base misprediction history register. The branch prediction apparatus includes a meta predictor that receives an index value and a branch prediction to generate a misprediction value in accordance with the base misprediction history register. The branch prediction apparatus also includes a logic gate that receives the branch prediction and the misprediction value to generate a final prediction. The final prediction may be used to predict whether a branch is taken or not taken.

Method and apparatus for predicting branches using a meta predictor

A memory cache bank prediction unit is provided for use in a processor having a plurality of memory cache banks. The memory cache bank prediction unit has an input port that receives an instruction. The memory cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of memory cache banks is associated with the instruction.

Memory cache bank prediction

A system and method for recovering from mispredicted paths in pipelined computer architectures. Targets within an instruction window exhibit spatial locality. To exploit this property, a mechanism detects the branch target within the instruction window. A second process eliminates the need for full renaming and re-execution of mispredicted paths by handling a dependency chain of instructions.

Fast branch misprediction recovery method and system

The present invention is directed to a computer system and method for early resolution of a set of critical instructions. The computer system may include a scoreboard, a scheduling window and a confidence predictor. The scoreboard may include a set of reservation stations. Each one of the set of reservation stations may correspond to one of a set of decoded instructions. Each one of the set of reservation stations may have a priority field. The scheduling window may maintain the scoreboard, wherein if one of the set of decoded instructions is one of the set of critical instructions, the scheduling window may mark the priority field corresponding to the particular one of the set of decoded instructions and also may find and mark the priority field of each of a set of base instructions upon which the particular one of the set of decoded instructions depends. The confidence predictor may also be used to predict whether one of the set of decoded instructions is one of the set of critical instructions.

System and method for early resolution of low confidence branches and safe data cache accesses

A cache bank prediction unit is provided for use in a processor having a plurality of cache memory banks. The cache bank prediction unit has an input port that receives an instruction. The cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of cache banks is associated with the instruction.

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Cupertino, CA, United States of America

Mattan Erez