3dlabs Inc., Ltd.

Intergraph Corporation

Matt E Buckelew

James Leroy Deming

Steven James Heinrich

Clifford A Whitmore

Dale L Kirkland

Stewart G Carlton

Mark Allen Mosley

Timothy S Johnson

Michael S Farmer

An apparatus and method of displaying a first image on a display device with a plurality of pixels assigns one of a plurality of sample patterns to each pixel on the display device. Each pixel is assigned the one of a plurality of patterns based upon its unique location on the display device. Each sample pattern has at least one sample location. It then is determined if the first image intersects any of the sample locations on each pixel. Pixels determined to have at least one sample location that intersect the first image thus are illuminated.

System for reducing aliasing on a display device

A device for storing pixel information for displaying a graphics image on a display includes a frame buffer and a processor. The information includes an intensity value and a value associated with each of a plurality of additional planes for each pixel. The frame buffer memory has a series of consecutive addresses for storing information to be output to the display. The frame buffer may be subdivided into a plurality of blocks, where each block corresponds to a region of the display having a plurality of contiguous pixels. The processor places the pixel information within the frame buffer memory so that in a given block there are placed at a first collection of consecutive addresses the intensity values for each of the pixels in the block.

High speed video frame buffer

An apparatus for displaying a polygon on a horizontal scan display device having a plurality of pixels includes first and second rasterizers that each process respective first and second sets of pixels. Each set of pixels includes vertical stripes that are transverse to the horizontal scan of the display. To that end, the first rasterizer has an input for receiving polygon data relating to the polygon. The first rasterizer determines a first set of pixels that are to be lit for display of the polygon, and also determines display characteristics of the first set of pixels. Similar manner, the second rasterizer also includes an input for receiving polygon data relating to the polygon. The second rasterizer similarly determines a second set of pixels that are to be lit for display of the polygon, and also determines display characteristics of the second set of pixels. The first and second sets of pixels have no common pixels and are vertical stripes of pixels on the display device that are transverse to the direction of the horizontal scan.

Multi-processor graphics accelerator

An apparatus for displaying a polygon on a horizontal scan display device having a plurality of pixels includes first and second rasterizers that each process respective first and second sets of pixels. Each set of pixels includes vertical stripes that are transverse to the horizontal scan of the display. To that end, the first rasterizer has an input for receiving polygon data relating to the polygon. The first rasterizer determines a first set of pixels that are to be lit for display of the polygon, and also determines display characteristics of the first set of pixels. In a similar manner, the second rasterizer also includes an input for receiving polygon data relating to the polygon. The second rasterizer similarly determines a second set of pixels that are to be lit for display of the polygon, and also determines display characteristics of the second set of pixels. The first and second sets of pixels have no common pixels and are vertical stripes of pixels on the display device that are transverse to the direction of the horizontal scan.

This invention relates to providing high-speed video graphics through use of single ported memory chips on the video card.

Growing community of inventors

Madison, AL, United States of America

Matt E Buckelew