Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Sandisk Corporation

Matt Davidson

Baojing Liu

Aruna Gutta

Vladimir Kovalev

Eran Erez

Gary Lin

Milton Lourenco Barrocas

Nicholas Thomas

A storage system receives a command from a host to overwrite data that is stored in a memory of the storage system. The command may have been issued in error or by malware, so the storage system preserves the data that the host wants to overwrite, just in case the host later wants to recover the data. To do this, the storage system associates the physical address of the location of the memory that stores the data with a logical block address that is inaccessible by the host. To recover the data, the storage system replaces the logical block address that is inaccessible by the host with a logical block address that is accessible by the host.

Storage system and method for preserving overwritten data to allow a future rollback

Apparatus and methods implemented therein are disclosed for communicating with flash memories. The apparatus comprises a flash interface module and a processor in communication with the flash interface module. The flash interface module is configured for communication with a first and second flash bank. The processor is configured to generate a plurality of command sequences in response to receiving a plurality of flash commands from a host system. Each of the plurality of command sequences corresponds to a respective one of the plurality of flash commands. Some of the plurality of command sequences comprises a first portion and a second portion and each of the first portion and second portion are atomic. The processor associates each of the plurality of command sequences with a priority, and via the flash interface module, selects one of the plurality of the command sequences based on the priority associated with the one of the plurality of the command sequences and transmits sequentially the first portion of the one of the plurality of the command sequences to either one of the first flash bank or the second flash bank.

Method and system for communicating with non-volatile memory

First and second data interfaces provide data transfer to and from a plurality of memory banks. The first data interface uses a first bus size and a first clock frequency. The second data interface uses a second bus size and a second clock frequency. The second bus size is an integer multiple of the first bus size. The first clock frequency is an integer multiple of the second clock frequency. A channelizer module segments data from the second data interface into data segments of the first bus size and transmits them to addressed ones of the plurality of memory banks using the first clock frequency. The channelizer module also receives data in accordance with the first bus size and first clock frequency from the plurality of memory banks, combines this data into the second bus size, and transmits the data to the second data interface using the second clock frequency.

Memory access control module and associated methods

A soft-function trigger state machine includes state machine logic defined to use a scan-in waveform to sample a scan-clock waveform to obtain a sampled data pattern. The state machine logic is defined to compare the sampled data pattern to a soft action pattern to determine whether the sampled data pattern matches the soft action pattern. The state machine logic is also defined to trigger an action associated with the soft action pattern when the sampled data pattern matches the soft action pattern.

Test mode soft reset circuitry and methods

An integrated circuit chip includes a scan-in pin, a scan clock pin, and a test controller. The scan-in pin and the scan clock pin receive a test program for the type of test mode and a soft-reset pattern. A state machine is configured to direct sampling of a scan clock waveform provided through the scan clock pin as dictated by transitions of a scan-in waveform provided through the scan-in pin. The state machine identifies a bit match from the sampled scan clock waveform upon executing the soft-reset pattern. The identified bit match triggers a soft reset which eliminates the need for an extra reset pin, when testing in scan mode.

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Mountain View, CA, United States of America

Matt Davidson