Psemi Corporation

Peregrine Semiconductor Corporation

Matt Allison

Eric S Shapiro

Shashi Ketan Samal

Tero Tapio Ranta

Simon Edward Willard

Ravindranath D Shrivastava

Fleming Lam

Peter Bacon

Yuan Luo

Jay Kothari

Tran Kononova

Jacob Hamilton

Kim T Nguyen

Devices and methods to manufacture a stack of FET switches in presence of a neighboring stack of FET switches are described. The stack of FET switches is designed or manufactured so that at least its top FET has a width that is smaller than the width of its bottom FET. Other voltage handling configurations and distributions of widths are described.

Variable width for RF neighboring stacks

A FET switch stack and a method to operate a FET switch stack. The FET switch stack includes a stacked arrangement of body bypass FET switches connected across respective common body resistors. The body bypass FET switches bypass the respective common body resistors during the OFF steady state of the FET switch stack and do not bypass the respective common body resistors during the ON steady state.

Body resistor bypass for RF FET switch stack

A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an 'end-cap' FET of a type that turns OFF when its Vis zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero Vtype, or a mix of positive-logic and zero Vtype FETs with end-cap FETs of the zero Vtype. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

AC coupling modules for bias ladders

Method and devices to reduce integrated circuit fabrication process yield loss due to undesired interactions between PCMs and the wafer test probes during wafer sorting tests are disclosed. The described methods entail the use of a properly patterned metal layer on the PCM dies adjacent to the product dies under test. Such patterned metal layers shield traces of the wafer probes from the circuits of the PCM dies. Various exemplary metal layer patterns are also presented.

PCM metal shielding for wafer testing

Stacked FET switch bias ladders

Embodiments include a switch stack comprising ACS FETs and mixed-style gate resistor bias networks that mitigate the effects of high leakage current. By carefully selecting the number of ACS FETs in a sub-stack that uses a rung gate resistor bias network versus a sub-stack that uses a rail gate resistor bias network, as well as by selecting particularly useful values for the gate resistors in each bias network, a tradeoff can be achieved between adverse Vg offset and Q factor. The switch stack may be configured with rung-rail gate resistor bias networks, or with rung-rail-rung gate resistor bias networks. Other embodiments include mixed-style body resistor bias networks in switch stacks comprising non-ACS FETs. Some embodiments include one or more positive-logic FETs M1-Mn, series-coupled on at least one end to an 'end-cap' FET Mof a type that turns OFF when the applied Vis essentially zero volts.

Mixed style bias network for RF switch FET stacks

Embodiments of systems, methods, and apparatus for improving ESD performance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on Semiconductor-On-Insulator ('SOI') and Silicon-On-Sapphire ('SOS') substrates.

Floating body contact circuit method for improving ESD performance and switching speed

An electronic system that includes a digitally selectable phase shifter circuit and an insertion loss fine adjustment circuit such that the system as a whole exhibits little or no change in insertion loss when changing phase state, and/or a digitally selectable attenuator circuit and a phase fine adjustment circuit such that the system as a whole exhibits little or no effect on phase when changing attenuation state. Included are methods for selecting adjustment control words for such circuits.

State change stabilization in a phase shifter/attenuator circuit

A digitally controlled phase shifter and (optional) attenuator circuit that has both a broad range as well as a fine-tuning resolution. Embodiments maintain a full 360&#xb0; phase range while providing n-bit least-significant bit (LSB) resolution across the entire range of possible phase shift and attenuation states, and compensate for the effect of frequency and/or PVT variations. In embodiments, two or more range partitionings can be defined that can be monotonic over respective sub-ranges while providing full coverage when combined. One such partitioning is a 'coarse+fine' architecture. Embodiments of the coarse+fine architecture provide for greater than 360&#xb0; of range for phase shifting and more than the total nominal design level for attenuation, and provide for fine ranges for both phase shifting and attenuation that are greater than the LSB of the corresponding coarse ranges for phase shifting and attenuation.

Fine and coarse phase and amplitude control

Embodiments of systems, methods, and apparatus for improving ESD tolerance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on semiconductor-on-insulator and silicon-on-sapphire substrates. Embodiments provide an improved FET structure having an accumulated charge sink (ACS) circuit, fast switching times, and improved ESD tolerance.

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Oceanside, CA, United States of America

Matt Allison