Fujitsu Corporation

Fujitsu Vlsi Limited

Matsuju Yoshida

Hiroko Murakami

Takaaki Ido

Kenzi Yamada

A first selector outputs either an output of an ALU (arithmetic logic unit) or a first clipped value to a first bus. A temporary register holds the output signal of the ALU, and a second selector outputs either the output signal of the temporary register or a second clipped value. A controller causes an operation result regarding lower data of first and second operands to be stored in the temporary register in a first cycle of the ALU when each of the first and second operands consists of 2n bits while the ALU operates on n bits per cycle thereof. When an operation result regarding upper data of the first and second operands overflows in a second cycle of the ALU, the controller causes the first and second selectors to output the first and second clipped values. When the operation result regarding the upper data does not overflow, the controller causes the first and second selector to respectively output the output signals of the ALU and the temporary register.

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Kasugai, Japan

Matsuju Yoshida