Telefonaktiebolaget Lm Ericsson (publ)

Mats Olof Joakim Hedberg

Tord L Haulin

In a differential line receiver circuit having differential amplifier circuit where output rise and fall times are influenced by the ability of internal current sources to charge parasitic capacitances, a feedback circuit is provided to tune those current sources so as to deliver equal rise and fall time on both outputs. According to one embodiment a detector signal is derived from timing errors resulting from such rise and fall time discrepancies by means of a nested CMOS inverter arrangement coupled to an integrating element, and then used to control one or both of said current sources. It is further disclosed how deviations in the center voltage of the internal power supplies caused by the current source tuning can be allowed for by pre-processing of the signal at the input of the differential line receiver circuit by means of a differential signal transfer circuit which is able to impose a common mode signal on the input signal so as to match the center voltage of the differential amplifiers internal power supply.

Differential line receiver

A differential signal transfer circuit to control the common mode level of a differential signal, comprising an input common mode level detection circuit, for detecting the common mode level of an incoming signal, two capacitors coupled between the first input and output and the second input and output respectively, and a control circuit adapted to control an output common mode voltage level at the output terminals by controlling the levels of charge on the two capacitors dependent on the common mode level of the incoming signal as detected by the input common mode detector.

Differential signal transfer circuit

A digital line driver circuit for driving a transmission line and being arranged to receive a digital input signal Di and output a digital output signal in accordance with said digital input signal Di, said digital line driver circuit being operable in at least a first and a second mode in accordance with a mode selection signal Pe, wherein said first mode is a signal relay mode in which said digital output signal follows said digital input signal, and said second mode is a pre-emphasis mode in which said digital output signal follows said digital input signal and has an additional predetermined distortion.

Digital line driver circuit

A connecting arrangement includes a number of NMOS transistors that can be activated or deactivated by means of a control voltage, serving as a control signal, connected to the gate terminals of transistors, to be able to form a circuit connected between two conductors, the circuit presenting resistive properties. The circuit is equipped with a signal receiver and it is regulated by an analog control voltage. The control voltage is connectable to one or several of a number of available control connections. Each control connection is connected to the gate terminals of a group of transistors where the drain and source terminals are connected to the conductors. The control voltage is selected so that the operating point of the transistors will be within, or at least close to, the region where the transistor presents resistive properties.

Growing community of inventors

Haninge, Sweden

Mats Olof Joakim Hedberg