Telefonaktiebolaget Lm Ericsson (publ)

Mats Goran Wilhelmsson

Peter Carl Lundh

Anders Bjenne

Clarence J&ouml;rn Niklas Fransson

Clarence Jorn Fransson

Rolf M&aring;rtensson

A phase locked loop includes at least one control circuit, where a voltage-controlled oscillator provides an output frequency which is arranged to strive to follow an input frequency. The phase locked loop also includes an outer, slow, negative feedback control circuit, having the input frequency as a setpoint, the output frequency as a process value and an outer output signal. The phase locked loop also includes an inner, fast, negative feedback control circuit, having the sum of a reference frequency from a stable oscillator and the outer output signal as a setpoint, the output frequency as the process value and an inner output signal for controlling the voltage controlled oscillator.

Phase locked loop control via inner and outer feedback control circuits

A phase-locked loop having very fast acquisition, and low output phase jitter and stability at steady-state is provided. In general, the phase-locked loop is used for synchronizing an output signal of said phase-locked loop with an input reference signal. The filter circuit of the phase-locked loop includes a differentiator responsive to the phase difference representing signal from a phase detector in the PLL for providing a differentiated signal, and a filter responsive to both the phase difference representing signal and the differentiated signal to provide a filter output signal. Preferably, the filter is a low-pass filter. The output signal source of the PLL is controlled by a control signal which is generally based on the filter output signal.

Phase locked loop

In a network, such as a large telecommunication switch, intended for the processing of information in different stations and for transmitting information between the stations, centrally located circuits are provided, which independently generate clock signals containing both a system clock rate and a frame synchronizing rate. These clock signals are transmitted on several, in the preferred case three, different transmission lines to a station where a multiplexor makes a selection of a clock signal as controlled by evaluation circuits containing circuits for determining errors in the received clock signals and also containing a state machine. The multiplexor selects periodically and repeatedly all the time a new clock signal in a cyclical pattern, which is accomplished by temporary, very short errors that are introduced when generating the issued clock signals. Thereby certainly all the time small phase jumps are introduced in the selected clock signal but at the same time the magnitude is reduced of a phase jump in relation to the former average phase position of the selected clock signal when possibly one of the incoming clock signals cannot be selected any more.

Clock selector system

In a network, such as a large telecommunication switch, intended for the processing of information in different stations and for transmitting information between the stations, circuits are provided which generate independently composite clock signals containing both a clocking rate and a frame synchronizing rate. These clock signals are transmitted on three different transmission lines in parallel and independently to a station, where some kind of information processing is made in redundant planes. In the station all incoming clock signals are fed to each one of three independently operating selector units in which a choice of a clock signal is made for obtaining a clock signal to be used in the three redundant planes arranged in parallel to each other and operating independently of each other, in the station.

Operation and maintenance of clock distribution networks having redundancy

A phase detector for measuring phase differences between K input signals is provided. The phase detector includes a counter, K first registers and a first subtractor. Each first register receives the counter signal of the counter and a respective input signal for updating a counter value in response to timing information on the input signal. The first subtractor receives the counter values to generate phase difference representing values. A frequency detector is also provided. The first subtractor is substituted by a second subtractor and K second registers are included. Each second register is connected to a respective first register. Each second register receives the counter value of its first register and the same input signal as that of its first register for backing-up the counter value as a back-up counter value in response to the timing information on the input signal. The second subtractor subtracts, for each second register and its first register, the counter values thereof to generate a frequency representing value.

Phase and frequency detector with high resolution

A composite reference signal distributes with one single signal both a clock signal and a synchronizing signal. This synchronizing signal is detected in a subsequent bit clocking generator for a high bit clocking frequency. Jitter that may exist on the edges of the clock signal will not influence the definition of the locally obtained synchronizing signal, and each data bit frame defined by the synchronizing signal will always include the exact number of data bits at the bit clocking frequency. The bit clocking generator includes a phase-locked loop, a dividing circuit, a shift register, and a logic gate for generating from the composite signal the bit clocking signal with its frame reference. In addition to the bit clocking frequency, a synchronizing pulse is obtained from the bit clocking generator that has high precision in relation to both the high frequency system clock and an external time domain transferred through the composite reference signal.

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Stockholm, Sweden

Mats Goran Wilhelmsson