Inphi Corporation

Clariphy Communications, Inc.

Mcafee, Inc.

Marvell Asia Pte., Ltd.

Matias German Schnidrig

Mario Rafael Hueda

Damian Alfonso Morero

Mario Alejandro Castrillon

Facundo Abel Alcides Ramos

Oscar Ernesto Agazzi

Diego Ernesto Crivelli

Hugo Santiago Carrer

Norman L Swenson

Vadim Gutnik

Paul Voois

Ramiro Rogelio Lopez

Martin Ignacio Del Barco

Jorge Manuel Finochietto

Alfredo Javier Taddei

Mauro Marcelo Bruni

Federico Nicolas Paredes

Elvio Adrian Serrano

Martin Carlos Asinari

Pablo Gustavo Quiroga

Roman Antonio Arenas

Alejandro Javier Schwoykoski

Adrián Ulises Morales

María Laura Ferster

Maria Laura Ferster

Franco Paludi

Ulises Morales

Laura Maria Ferster

Teodoro Ariel Goette

A communication system includes a transmitter having an encoder configured to encode input data using FEC codewords and a receiver including a decoder configured to decode the FEC codewords using a parity check matrix. The decoder includes check node processing units each configured to perform a check node computation on an FEC codeword using a different row of the parity check matrix. Each of the check node processing units includes an input computation stage configured to compute initial computation values, a pipelined message memory configured to shift the initial computation values at a predefined clock interval, an output computation stage configured to generate a plurality of check node output messages, a plurality of variable node processing units each configured to perform variable node update computations to generate the variable node messages, and an output circuit configured to generate a decoded codeword based on the variable node messages.

Non-concatenated FEC codes for ultra-high speed optical transport networks

Methods, systems, and media for protecting against return-oriented programming malware are provided. In some embodiments, the method comprises: retrieving an executable module; identifying a basic block in the executable module located at a first memory location, wherein the basic block has one entry point and one exit point; moving a portion of the executable module that corresponds to the basic block to a random memory location from the first memory location; and replacing a destination of a function call to the basic block within the executable module with a representation of the random memory location.

Rearranging executables in memory to prevent rop attacks

A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

Coherent transceiver architecture

A decoder performs forward error correction based on quasi-cyclic regular column-partition low density parity check codes. A method for designing the parity check matrix reduces the number of short-cycles of the matrix to increase performance. An adaptive quantization post-processing technique further improves performance by eliminating error floors associated with the decoding. A parallel decoder architecture performs iterative decoding using a parallel pipelined architecture.

A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal at the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

Growing community of inventors

Bialet Masse, Argentina

Matias German Schnidrig