Alcatel Internetworking, (Pe), Inc.

Other

Mathieu Tallegas

Werner Van Hoof

Jerrold Wheeler

Abdelkahim Safir

A packet processor whose processing capabilities are optimized by concurrently processing multiple packets within various pipelined stages. At each stage, multiple packets are processed via an internally pipelined sub-processor. In one embodiment, the packets are processed in a round robin fashion. When a particular packet is done processing at a particular stage, it may pass another packet whose processing is not complete, and move to a next stage. In another embodiment, a packet is processed until a conditional branch instruction or any other instruction causing a potential stall is encountered. If such an instruction is encountered, a next available packet is selected and processed instead of wasting processing cycles during the stall, or proceeding with the processing of the current packet based on a predicted result. The sub-processor resumes processing of the packet once the stall is over.

Non-blocking, multi-context pipelined processor

Multiple lookup engines stacked upon one another in a single data communication switch. The lookup engine at the top of the stack transmits its result to the neighboring downstream lookup engine which either validates and transmits the received result or its own result based on the quality of its match. The result preferably indicates an exact match, partial match, or no match. Although several lookup engines can return a partial match, an exact match preferably occurs in only one lookup engine. The comparison, validation, and transmission steps are repeated by each downstream lookup engine, with the lookup engine at the bottom of the stack validating and returning a final result to the packet processor. The returned final result reflects a search result with the highest match quality.

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Veradale, WA, United States of America

Mathieu Tallegas