Nxp B.v.

Nxp Usa, Inc.

Mathieu Périn

Stefano Dal Toso

Khurram Waheed

Vijay Ahirwar

Philippe Christian Belin

Mathieu Vallet

Laurent Gambus

A method of operation for a dual mode Phase-Locked Loop (PLL) for phase coherent application includes selecting one of a non-coherent mode and a coherent mode. The non-coherent mode includes controlling a Voltage Controlled Oscillator (VCO) with a first error voltage determined by a first Low Pass Filter (LPF), the first LPF configured to filter a first output of a phase detector, the phase detector configured to determine a phase difference between a reference frequency and a feedback signal derived from a VCO frequency generated by the VCO. The coherent mode includes controlling the VCO with the first error voltage and a second error voltage determined by a second LPF of a Proportional and Integral Controller (PIC) configured to filter the first output of the phase detector and by a time variant proportional gain configured to modify a second output of the second LPF.

Dual mode PLL for phase coherent application

A transmit apparatus comprising a scaler arranged to scale a frequency deviation signal associated with a frequency shift keying signal (FSK) by a scale factor and a limiter arranged to limit frequency deviations of the scaled frequency deviation signal after a filtering. A power spectral density, phase trajectory, and frequency deviation of an FSK signal based on the limited scaled frequency deviation tracks similar criteria of a minimum phase shift keying (MSK) signal.

Transmit apparatus arranged to scale and limit frequency deviation generated after a filtering based on a frequency shift keying (FSK) signal and methods of operation

An analog PLL comprising: a VCO configured to provide a PLL output signal; a phase detector (PD) configured to receive a feedback signal from the VCO and a reference signal and wherein the PD provides a PD signal to a low pass filter (LPF), the LPF configured to filter of the PD signal and provide the filtered signal as a tuning voltage for the VCO; and a tracking loop configured to receive the tuning voltage and comprising at least a tracking loop comparator configured to provide a comparator output voltage based on a difference between the tuning voltage and a target voltage, wherein an output of the tracking loop provides a tracking voltage based on the comparator output voltage and wherein the frequency of the PLL output voltage is based on the tuning voltage and the tracking voltage.

Analog phase locked loop

A duty cycle correction circuit (DCCC) for a multi-modulus frequency divider, the DCCC comprising: a corrector chain comprising a plurality of flip-flops each configured to receive one of the internal signals; and at least one delay selection logic element, each configured to receive an output signal from different ones of the flip-flops and the output of each delay selection logic element is based on the received output signal and the division factor; the DCCC is configured such that: a first state change in its output signal is defined by a transition to a first logic state of one of the internal signals; and a second state change in its output signal is based on a transition to a second logic state of one of the internal signals after a delay period, wherein the duty cycle of the output signal is based on the delay period.

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Cairon, France

Mathieu Périn