Pmc-sierra Us, Inc.

Cadence Design Systems, Inc.

Pmc-sierra, Inc.

Microsemi Storage Solutions (u.s.), Inc.

Microsemi Storage Solutions, Inc.

Mathieu Gagnon

Guillaume Fortin

Charles Roy

Jean-Francois Delage

Paul Borsetti, Jr

Anthony Eugene Zortea

Eric Harris Naviasky

Winston Ki-Cheong Mok

Graeme Barclay Boyd

Jurgen Hissen

Julien Faucher

Louis-Francois Tanguay

Santiago Luis Bortman

Brett Clark

Atit Patel

Mathew McAdam

Cindy Mark

Various embodiments provide a method or system that implements a two-tap decision feedback equalizer by applying a first tap and a second tap on a first symbol of a data signal, each of the first and second taps having a first and second polarity to generate a first corrected data symbol and a second corrected data symbol. The first corrected data symbol and the second corrected data symbol is provided to a comparator to select a data symbol. The output of the comparator is provided to a clock data recovery circuit along with a previous data symbol of the data signal preceding the first data symbol.

Digital filter for second tap of DFE

Various embodiments described herein provide for a receiver device that includes a processor, a non-linear equalizer, an accumulation register, and a plurality of co-processors. Each of the plurality of co-processors is operably coupled to the processor, the non-linear equalizer, and the accumulation register. Each of the plurality of co-processors can be configured to receive a configuration value from the processor, receive a data signal for processing from the non-linear equalizer, process the data signal based on the configuration value, and provide at least a portion of the processed data signal to the processor.

Programmable correlation computation system

Various embodiments provide for quarter-rate data sampling with loop-unrolled decision feedback equalization (DFE) that uses a two-summer (e.g., two-summing node) approach. For example, some embodiments provide for quarter-rate data sampling comprising a plurality of unrolled first-tap DFE loops, and two summers and a two-to-one multiplexer for each of the other tap loops used for direct feedback (e.g., second tap, third tap, fourth tap, etc.)

Quarter-rate data sampling with loop-unrolled decision feedback equalization

A receiver device includes circuitry and memory. The circuitry converts an input signal into a data signal that includes data symbols transmitted in successive unit intervals (UIs), determines a first threshold associated with a first symbol type, adjusts a gain of the receiver device such that an average amplitude of data signal samples, when receiving data symbols having the first symbol type, corresponds to the first threshold, determines a second threshold that corresponds to an average amplitude of the data signal samples when data symbols of a current UI have the first symbol type and data symbols of a first UI, at a first determined time distance from the current UI, have a second symbol type, and computes, as a first cursor value associated with the first UI, a first difference between the first threshold and the second threshold, multiplied by a first constant.

System and method for measurement and adaptation of pulse response cursors to non zero values

A system and a method for detecting a low-frequency periodic signal (LFPS) include at least one comparator performing a threshold comparison on an analog input signal over a period of time. A sampling circuit generates digital signals by sampling an output of the at least one comparator. A digital detection circuit applies a set of detection rules to the digital signals. The detection rules are configured to detect a presence or an absence of an LFPS based on predefined criteria concerning characteristics of the digital signals.

Low-frequency periodic signal detector

A method and system for encoding ancillary information at a transmitter in a high-speed communications network, the method comprising: generating an electromagnetic interference (EMI) reduction signal; receiving an ancillary data symbol; generating an EMI reduction signal variation based on the ancillary data symbol; and varying a characteristic of the EMI reduction signal based on the generated EMI reduction signal variation to encode the ancillary data symbol in the varied EMI reduction signal.

System and method for transmitting ancillary data

The present disclosure relates to a method and apparatus for detecting clock and data recovery loop saddle-point locking in an electronic circuit. Embodiments may include receiving a signal at a primary clock and data recovery ('CDR') loop associated with the electronic circuit and processing the signal using at least one of a first order CDR loop and a second order CDR loop included within the primary CDR loop. Embodiments may further include determining whether a fast-phase lock module is required, wherein determining includes determining two transitions in a sampling triplet. If it is determined that the fast-phase lock module is required, embodiments may include providing a trigger signal to the fast-phase lock module. Embodiments may further include receiving the trigger signal at the fast-phase lock module associated with the electronic circuit and performing a fast-phase lock operation on the signal.

System and method for saddle point locking detection during clock and data recovery

Apparatus and methods advantageously maintain transistors of open-drain differential pairs biased in the saturation region when 'active,' rather in than the triode or linear region. The biasing techniques are effective over a broad range of process, voltage, and temperature (PVT) variations. By controlling a high voltage level used to drive the gate of a transistor of the differential pair, the biasing of the transistor in the saturation region is maintained. In one embodiment, the low voltage level used to cut off the transistor of the differential pair is also controlled. These techniques advantageously permit differential drivers to exhibit relatively large output swings, relatively high edge rates, relatively high return loss, and relatively good efficiency.

Active biasing in metal oxide semiconductor (MOS) differential pairs

A method and apparatus for timing optimization are disclosed, which rely on information gathered from a timing detection circuit to find the optimal sampling point of a data recovery system. In an implementation, a timing shift is optimized based on Gardner detector data. In an example, a Gardner detector, or an early and late extraction portion thereof, is added to the data path, and the data path clock is shifted so that it is centered on the data transition mean. In an implementation, the sampling point of the data path is optimized for better horizontal eye opening using a Gardner detector's output for centering the average crossing point of different paths. In an example embodiment, an apparatus is provided with a second clock recovery that is not completely independent of a first clock recovery.

Method and apparatus for sampling point optimization

A link negotiation method for enabling communication between first and second Serial Attached Small Computer Interface (SAS) storage devices operably coupled by an optical cable. The method includes continuously transmitting a non-SAS data pattern between the first and second SAS storage devices. In response to successful exchange of the non-SAS data between the first and second SAS storage devices, a SAS data pattern is continuously transmitted between the first and second SAS storage devices. In response to successful exchange of the SAS data pattern between the first and second SAS storage devices, an initial frame is continuously transmitted between the first and second SAS storage devices. Communication between the first and second SAS storage devices is enabled in response successful communication of the initial frame between the first and second SAS storage devices.

Link negotiation method for enabling communication between serial attached small computer interface (SAS) storage devices

An unrolled decision feedback equalizer (DFE) as disclosed herein has a reduced number of compensation factors while keeping a suitable performance level for a given application. The Kpossible DFE correction levels are reduced or compressed into fewer levels (R), merging together the levels that are the closest together where K represents the number of possible symbols in each baud, or the number of bits encoded into each baud, and N represents the DFE depth in number of bauds. A mapping function is then provided to convert the Kcombinations of previous history bits into R sampler selections.

Compensation factor reduction in an unrolled decision feedback equalizer

An equalization adaptation circuit comprises an equalizer, a transition determination circuit, a phase error circuit, a sequence recovery circuit, a phase error accumulator circuit, a transition accumulator circuit, and a controller circuit. The equalizer has adjustable parameters. The transition determination circuit determines observed transitions in an equalized signal output from the equalizer. A phase error circuit determines phase errors of the observed transitions. A sequence recovery circuit generates recovered digital data sequences. A phase error accumulator circuit accumulates the phase errors in respective association with pre-defined patterns matching the recovered digital data sequences containing observed transitions corresponding to the phase errors. A transition accumulator circuit accumulates a number of the observed transitions. A controller circuit controls the adjustable parameters of the equalizer based upon the accumulated phase errors and number of observed transitions.

Equalization adaptation using timing detector

An equalizer is disclosed, and associated operational method. The equalizer has a configuration that balances performance and complexity by obtaining samples that are strongly correlated with future and past transmitted bits, and are weakly correlated with future and past bit transitions, and is useful for timing recovery circuits. Samples are only obtained or collected at time intervals more than one sample period away from the reference sample. Samples are shifted by a delay value less than the sample period, and are obtained at a sample period of one unit interval. A means to adjust the sampling point delay is also disclosed. In an implementation, samples that are within the sample period away from the reference sample are obtained and used for implementing a timing shift, not for equalization of the timing recovery signal. Embodiments are also disclosed for optimizing performance for data recovery.

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Verdun, Canada

Mathieu Gagnon