Infineon Technologies Ag

Infineon Technologies Austria Ag

Mathias Plappert

Andreas Riegler

Angelika Koprowski

Hans-Joachim Schulze

Frank Wolter

Stefan Krivec

Joachim Hirschler

Markus Heinrici

Christoffer Erbert

Frank Dieter Pfirsch

Michael Hutzler

Stephan Voss

Alexander Breymesser

Michael Roesner

Carsten Schaeffer

Olaf Storbeck

Georg Ehrentraut

Thomas Gutt

Dorothea Werber

Oliver Humbel

Ingmar Neumann

Caterina Travan

Karin Schrettlinger

Carsten Schäffer

Wolfgang Koell

Eva-Maria Hof

Klaus Goeschl

A semiconductor device and a method of manufacturing a semiconductor are provided. In an embodiment, a metallic layer may be formed over a semiconductor substrate. An anti-reflective layer may be formed over the metallic layer. A passivation layer may be formed over the anti-reflective layer. An opening may be formed in the passivation layer to expose the anti-reflective layer.

Semiconductor device protection using an anti-reflective layer

In one aspect, a method of forming a silicon-insulator layer is provided. The method includes arranging a silicon structure in a plasma etch process chamber and applying a plasma to the silicon structure in the plasma etch process chamber at a temperature of the silicon structure equal to or below 100&#xb0; C. The plasma includes a component and a halogen derivate, thereby forming the silicon-insulator layer. The silicon-insulator layer includes silicon and the component. In another aspect, a semiconductor device is provided having a silicon-insulator layer formed by the method.

Methods of forming a silicon-insulator layer and semiconductor device having the same

A method for forming a semiconductor device and semiconductor device is disclosed. In one example, the method includes forming a silicone layer on a semiconductor die. The method further includes plasma treating a silicone surface of the silicone layer. A surfactant is deposited on the plasma-treated silicone surface of the silicone layer to obtain a silicone surface at least partly covered by surfactant. A mold is formed on the silicone surface at least partly covered by surfactant. The surfactant includes surfactant molecules comprising an inorganic skeleton terminated by organic compounds.

Methods for forming semiconductor devices and semiconductor device

In various embodiments, a method is provided. The method includes forming a metallization layer above at least one first region of a substrate. After forming the metallization layer at least one second region of the substrate is free of the metallization layer. The method further includes forming a barrier layer above the at least one first region of the substrate and above the at least one second region of the substrate. The barrier layer in the at least one first region of the substrate directly adjoins the metallization layer. The method further includes removing the barrier layer in the at least one first region of the substrate by drive-in of the barrier layer into the metallization layer.

Semiconductor component, method for processing a substrate and method for producing a semiconductor component

A semiconductor arrangement is presented. The semiconductor arrangement comprises a semiconductor body, the semiconductor body including a semiconductor drift region, wherein the semiconductor drift region has dopants of a first conductivity type; a first semiconductor sense region and a second semiconductor sense region, wherein each of the first semiconductor sense region and the second semiconductor sense region is electrically connected to the semiconductor drift region and has dopants of a second conductivity type different from said first conductivity type; a first metal contact comprising a first metal material, the first metal contact being in contact with the first semiconductor sense region, wherein a transition between the first metal contact and the first semiconductor sense region forms a first metal-to-semiconductor transition; a second metal contact comprising a second metal material different from said first metal material, the second metal contact being separated from the first metal contact and in contact with the second semiconductor sense region, a transition between the second metal contact and the second semiconductor sense region forming a second metal-to-semiconductor transition different from said first metal-to-semiconductor transition; first electrical transmission means, the first electrical transmission means being arranged and configured for providing a first sense signal derived from an electrical parameter of the first metal contact to a first signal input of a sense signal processing unit; and second electrical transmission means separated from said first electrical transmission means, the second electrical transmission means being arranged and configured for providing a second sense signal derived from an electrical parameter of the second metal contact to a second signal input of said sense signal processing unit.

Sensor for a semiconductor device

A semiconductor device includes a semiconductor substrate having a first side, a second side opposite the first side, an active area, an outer rim, and an edge termination area arranged between the outer rim and the active area. A metallization structure is arranged on the first side of the semiconductor substrate and comprising at least a first metal layer comprised of a first metallic material and a second metal layer comprised of a second metallic material, wherein the first metallic material is electrochemically more stable than the second metallic material. The first metal layer extends laterally further towards the outer rim than the second metal layer.

Semiconductor device having a corrosion-resistant metallization and method for manufacturing thereof

An IGBT includes a semiconductor portion with IGBT cells. Each IGBT cell includes a source zone of a first conductivity type, a body zone of a second, complementary conductivity type, and a drift zone of the first conductivity type separated from the source zone by the body zone. An emitter electrode includes a main layer and an interface layer. The interface layer directly adjoins at least one of the body zone and a supplementary zone of the second conductivity type. A contact resistance between the semiconductor portion and the interface layer is higher than between the semiconductor portion and a material of the main layer. For example, the interface layer may reduce diode emitter efficiency and reverse recovery losses in IGBTs.

IGBT with emitter electrode electrically connected with an impurity zone

According to an embodiment, a method for manufacturing a semiconductor structure includes providing a first monocrystalline semiconductor portion having a first lattice constant in a reference direction and forming a second monocrystalline semiconductor portion having a second lattice constant in the reference direction, which is different to the first lattice constant, on the first monocrystalline semiconductor portion.

Method for manufacturing a semiconductor structure

According to an embodiment, a semiconductor structure includes a first monocrystalline semiconductor portion having a first lattice constant in a reference direction; a second monocrystalline semiconductor portion having a second lattice constant in the reference direction, which is different to the first lattice constant, on the first monocrystalline semiconductor portion; and a metal layer formed on and in contact with the second monocrystalline semiconductor portion.

Semiconductor structure, semiconductor device having a semiconductor structure, and method for manufacturing a semiconductor structure

Growing community of inventors

Villach, Austria

Mathias Plappert