Qualcomm Incorporated

Apple Inc.

Mathias Kohlenz

Shailesh Maheshwari

Thomas Klingenbrunn

Idreas Mir

Irfan Anwar Khan

Sandeep Urgaonkar

Srividhya Krishnamoorthy

Tim Liou

Vijay Venkataraman

Uppinder Singh Babbar

Martin Kugler

Ahmed Soud Salem

Sathyanarayan Madhusudan

Gavin Bernard Horn

Srinivasan Balasubramanian

Arnaud Meylan

Aziz Gholmieh

Sitaramanjaneyulu Kanamarlapudi

Amir Aminzadeh Gohari

Marcello Vincenzo Lioy

Bao Vinh Nguyen

Vanitha Aravamudhan Kumar

Vishal Dalmiya

Xiaoning Nie

Daisuke Terasawa

Alok Mitra

Yue Yang

Jean-Marie Tran

Vaibhav Kumar

Gurvinder Singh Chhabra

Samson Jim

Sriram Narayan

Vikas Nagpal

Madhusudan Sathyanarayan

Iain Finlay

Jin-Soo Yoo

Mohammed M Rumi

Gautam Sheoran

Shailesh Maheswari

Irfan A Khan

Jean-Marie Qd Tran

This disclosure relates to techniques for performing wireless communications including filtering packets for transmission between a user equipment (UE) and a base station. Techniques for filtering packets, at a lower layer and/or baseband processor, using higher layer information, such as a flow identifier, are disclosed. A device may generate various tables and may use the tables to filter packets efficiently.

Enhanced packet filtering

A merge sort circuit can include a parallel merge sort core that performs a partial merge on two input tuples, each containing a number P of data elements sorted according to a sort key, to produce a sorted output tuple of P data elements. Input data blocks to be merged can be stored in first and second block buffers. The block buffers can receive data from a vector memory read interface that reads groups of at least P data elements at a time. Loading of data elements into the block buffers can be based on respective fill levels of the block buffers.

Parallel merge sorter circuit

This disclosure relates to techniques for performing wireless communications including filtering packets for transmission between a user equipment (UE) and a base station. Techniques for filtering packets using higher layer information, such as a flow identifier, are disclosed. A device may generate various tables and may use the tables to filter packets efficiently.

Certain aspects of the present disclosure relate to wireless communications, and more particularly, to techniques for preparing data for transmission from a user equipment in a wireless communication system. In some embodiments, a method may limit memory access starts during a time interval to ensure that all memory access operations are completed with a transmission time interval.

Scheduling of uplink transport blocks

Aspects of the present disclosure provide methods and apparatus for offloading checksum processing in a user equipment (UE) (e.g., from an application processor to a modem processor). Such offloading may speed up packet processing, increase data rate, and/or free up resources of the application processor for other tasks.

Methods and apparatus for offloading checksum processing

Efficient data processing apparatus and methods include hardware components which are pre-programmed by software. Each hardware component triggers the other to complete its tasks. After the final pre-programmed hardware task is complete, the hardware component issues a software interrupt.

Data mover moving data to accelerator for processing and returning result data based on instruction received from a processor utilizing software and hardware interrupts

Systems and methods for wireless communications are provided. These include data deciphering components, interrupt processing components, adaptive aggregations methods, optimized data path processing, buffer pool processing, application processing where data is formatted in a suitable format for a destination process, and Keystream bank processing among other hardware acceleration features. Such systems and methods are provided to simplify logic designs and mitigate processing steps during wireless network data processing.

Hardware acceleration for WWAN technologies

Multiple memory pools are defined in hardware for operating on data. At least one memory pool has a lower latency that the other memory pools. Hardware components operate directly on data in the lower latency memory pool.

Apparatus and method for memory management and efficient data processing

Incoming data frames are parsed by a hardware component. Headers are extracted and stored in a first location along with a pointer to the associated payload. Payloads are stored in a single, contiguous memory location.

Apparatus and method for efficient memory allocation

Growing community of inventors

San Diego, CA, United States of America

Mathias Kohlenz