Artesyn Embedded Computing, Inc.

Mathias Hellwig

A system includes a first node that generates a first clock signal having a frequency, generates a plurality of data packets, modifies the data packets to include data indicative of time and phase information associated with the first node, and transmits the data packets. A second node receives the plurality of data packets and the first clock signal, determines the time and phase information based on the plurality of data packets, determines the frequency based on the first clock signal, and generates at least one of a second clock signal and a local time based on the time and phase information and the frequency of the first clock signal.

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Eichenau, Germany

Mathias Hellwig