Atmel Corporation

Linear Technology Corporation

Analog Devices International Unlimited Company

Mathew Todd Wich

Albert M Wu

Daniel Scott Cohen

Yanfeng Lu

Jason Joseph Ziomek

Vincent Gosmain

Rocendo Bracamontes

David W Dressen

Stephen Todd Van Duyne

Shude Lu

Fu Sun

Xiaohua Su

Techniques for efficient operation of a linear stage in an H-bridge system are provided. In an example, a linear stage can switch between voltage regulation and current regulation over a range of a command signal. The particular regulation mode can depend on the regulation mode of a switched stage of the H-bridge system. Efficiency can be realized by using current regulation of the linear stage when the output voltage of the linear stage moves away from the voltage of a supply rail. Such a control scheme can reduce the voltage across the linear stage for a larger range of the command signal resulting in less heat dissipation of the linear stage compared to conventional control of H-bridge linear stages.

Linear stage efficiency techniques for H-bridge systems

An error amplifier may be part of a voltage regulator and may include a single feedback input configured to receive a feedback signal. A single error output may be configured to provide an error output signal indicative of error in the feedback signal. A comparison circuit may be configured to provide an error signal to the single error output which is indicative of a difference between the feedback signal and whichever one of a set of reference signals is closest to the feedback signal. One or more of these reference signals may each be derived from an offset from a ground reference. One or more of the other reference signals may each be derived from an offset from a non-ground reference, such as a source of power for the error amplifier. The error amplifier may be on a single integrated circuit along with an associated driver circuit.

Error amplifier for regulating single feedback input at multiple levels

A digital control system including a microcontroller for handling timed events, a command decoder for interpreting user commands, a separate burst controller for handling burst reads of the Flash memory, a program buffer for handling page writes to the Flash memory, a page transfer controller for handling data transfers from the Flash core to the program buffer as well as address control for page writes from the program buffer to the Flash memory, a memory control register block for storing and adjusting memory control and memory test mode signals, a memory plane interface for multiplexing addresses into the Flash memory and accelerating program, erase, and recovery verification, and an I/O Mux module for multiplexing data out of the system, and a general purpose I/O port (GPIO) that can be read and written by the microcontroller for use in test and debug.

Microcontroller based flash memory digital controller system

A charge pump clock circuit for a memory device generates pump clock signals at an adaptive rate. Clock edges are generated at a minimum of Tseconds apart so long as address transitions do not exceed a pre-determined limit. However, if address changes are occurring more frequently than this limit, i.e., 1/(2*T), then clock edges will be generated at a rate that is proportional to the rate of address changes, where Tis approximately half of the address period. Two logic rules are implemented in hardware or equivalent software to make the clock signal adjustments.

Charge pump clock for non-volatile memories

In a voltage-level shifter, an input line is configured to convey an input voltage to be shifted. A pair of transistors is coupled to and is configured to receive the input voltage from the input line. There is a first side and a second side, with each side comprising the following: a low-voltage transistor that is coupled to the pair of transistors, a medium-voltage transistor that is coupled to the low-voltage transistor, a high-voltage transistor that is coupled to the medium-voltage transistor, and an output line, which is coupled to the first and second sides, for providing an output voltage that is higher than the input voltage.

Voltage-level shifter

An RFID interface integrated-circuit chip has three ports including a bi-directional RF port, a serial or parallel data external memory IC port, and a serial or parallel data external electronic system port. DC power is supplied to a separate external memory IC chip through the serial external memory port either from power obtained from an RF signal through the bi-directional RF port, from DC power provided from an external electronic system, or from an auxiliary voltage source, such as a battery or fuel cell that replaces power provided from the RF signal. Data and control signals are interchanged with the separate external memory IC chip through the serial or parallel external-memory port using the RF port when the external electronic system is not available or through the external electronic system serial or parallel port when the external electronic system is available.

Three port RF interface chip

An antifuse programming, protection, and sensing device incorporates a control circuit to program and protect an antifuse. The antifuse, which is initially constructed as a low conductivity path, is programmable to a high conductivity path by application of an elevated voltage across terminals of the antifuse. Application of 0 volts to the Vnode of a conduction control portion of the antifuse programming, protection, and sensing device allows an elevated voltage for programming to be applied to the antifuse. Upon application of a nominal working voltage to the Vnode of the conduction control circuitry, the antifuse and an adjoining sense amplifier circuit are protected from overvoltage and tampering. The sense amplifier supplies a sense current to the antifuse, measures a voltage at an input to the antifuse, and determines a programmed state if a measured voltage level is low.

Antifuse programming, protection, and sensing device

A charge pump clock for a memory device wherein pump clock signals are generated at an adaptive rate. The circuit of the present invention generates clock edges at a minimum of Tseconds apart so long as address transitions do not exceed a pre-determined limit. However, if address changes are occurring more frequently than this limit, i.e., 1/(2*T), then clock edges will be generated at a rate that is proportional to the rate of address changes, where Tis approximately half of the address period. Two logic rules are implemented in hardware or equivalent software to make the clock signal adjustments.

An on-chip interface circuit located between the chip's power supply pin and its internal circuitry senses the current load of the internal circuitry and provides a supplemental current sink so that total current demand seen at the power supply pin is substantially constant despite the internal circuitry's variable load. Sensing of the internal load is done by a sensor stage with two parallel branches, each branch having a resistor, a sense transistor, and a current mirror device, which together produce a voltage drop as a control voltage output which relates the internal load to a constant reference current. The supplemental current sink is in the form of a transistor operating below saturation in its linear region and whose gate is coupled to receive the control voltage output of the sensor stage.

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Colorado Springs, CO, United States of America

Mathew Todd Wich