Cypress Semiconductor Corporation

Micron Technology Incorporated

Mathew R Arcoleo

Cathal G Phelan

Ashish Pancholy

Simon J Lovett

Raymond M Leong

Derek R Johnson

Eugene Feng

Jonathan F Churchill

Rajesh Manapat

Neil P Raftery

Gary W Green

Piyush Sevalia

Scott Harmel

The present disclosure includes methods and apparatuses for read cache memory. One apparatus includes a read cache memory apparatus comprising a first DRAM array, a first and a second NAND array, and a controller configured to manage movement of data between the DRAM array and the first NAND array, and between the first NAND array and the second NAND array.

Data movement between volatile and non-volatile memory in a read cache memory

Read cache memory with DRAM class promotion

A device generally comprising a memory array and a burst sequence generator. The memory array may be configured to store data. The burst sequence generator may be configured to generate a burst sequence in response to address information received by the device. The burst sequence may be configured to identify a plurality of locations for storing data in the memory array. The device may have a maximum operating current of 50 milliamps and/or a maximum standby current of about 25 microamps.

Method and device for performing write operations to synchronous burst memory

A random access memory with a read port, a write port, a read/write control signal configured to control data transfer operations at the read port and/or the write port on both rising and falling transitions, and a first random access memory array configured to store and/or retrieve data at a first random address in the first random access memory array defined by one or more signals on a write address bus and/or a read address bus. One preferred embodiment further includes a write data register storing or latching data in response to a first transition of the read/write control signal, and the array storing data in response to a second transition of the read/write control signal. Other preferred embodiments further include an n&middot;m-bits-wide input data bus coupling a set of data inputs to the write data register, and/or an n&middot;m-bits-wide output data bus coupling the read data register to a set of data outputs, where n and m are each independently an integer >2.

Random access memory having independent read port and write port and process for writing to and reading from the same

A random access memory with a data input bus, a data output bus, a random access memory array configured to transfer data to random write addresses and from random read addresses in the random access memory array, an address bus providing the random read addresses and the random write addresses, and a first periodic signal configured to control data transfer operations (i) to the random access memory array in response to a first transition of the periodic signal and (ii) from the random access memory array in response to a second transition of the periodic signal, wherein the second transition of the periodic signal is complementary to the first transition of the periodic signal. One preferred embodiment further includes circuitry operable to write data into and read data from the random access memory array. Other preferred embodiments further include a write data register and/or a read data register. In a further embodiment, each of the data input bus and the data output bus is unidirectional. The invention also concerns a process for reading data from and writing data to a random access memory array.

Random access memory having a read/write address bus and process for writing to and reading from the same

A memory device includes an address pipeline configured to receive a write address at a first time and to provide the write address to a memory array at a second time, corresponding to a time when write data associated with the write address is available to be written to the array. The address pipeline may include a series of registers arranged to receive the write address and to provide the write address to the memory array. In addition, the memory device may include a comparator coupled to the address pipeline. The comparator is configured to compare the write address to another address (e.g., a read address) received at the memory device. A bypass path to the array may be provided for read addresses received at the memory device. A data pipeline is configured to receive data destined for the memory device and to provide the data to the memory array. The data pipeline may include a data bypass path which does not include the memory array.

Circuit architecture and method of writing data to a memory

Synchronous random access memory having a read/write address bus and process for writing to and reading from the same

A programmable skew buffer for optimizing the timing at the input or output pins of a memory device. The timing at each input and output pin of the memory device can be adjusted on an independent basis by coupling each input or output pin to a separate programmable skew buffer. The programmable skew buffer includes a clocked storage element that receives data from an input pin and outputs data to the memory array in the memory device when optimizing the input timing of the memory device, or receives data from the memory array in the memory device and outputs data to an output pin when optimizing the output timing of the memory device. The programmable skew buffer also includes a programmable delay circuit which generates one of a plurality of clock signals wherein each signal represents a delayed version of the system clock. The clock signal generated by the programmable delay circuit provides the input clock signal into the clocked storage element such that data is clocked into the clocked storage element in response to the input clock signal.

Programmably timed storage element for integrated circuit input/output

A memory array comprising a plurality of storage elements and a logic circuit. The memory array may be configured to (i) receive a plurality of input data streams, (ii) store each of the plurality of input data streams in one or more of the storage elements in response to a plurality of control signals and (iii) present a plurality of output data streams in response to the plurality of input data streams. The logic circuit may present the plurality of control signals in response to the fullness of each of the plurality of storage elements.

Cascadable multi-channel network memory with dynamic allocation

An output buffer circuit of a semiconductor memory device can produce multiple output buffer drive strengths. An electronic system including a memory device in which such an output buffer circuit is implemented can include a mechanism for enabling the output buffer drive strength to be easily selected by a user of the memory device (such as an assembler of an electronic system including the memory device) from the multiple possible drive strengths. The invention thus enables a memory device to be easily configured to have an output buffer drive strength that is compatible with a wide variety of electrical loads to be driven by the output buffers of the memory device. Since the output buffer circuit of the invention allows the output buffer drive strength to be more closely tailored to the electrical load being driven, signal reflections, voltage overshoot and undershoot, and timing problems that can result from mismatch between the output buffer drive strength and the associated electrical load can be reduced.

Memory having selectable output strength

A Static Random Access Memory (SRAM) comprises an input/output pin and driver means connected to the input/output pin. The driver means are configured to drive the input/output pin to a voltage potential using a first current, and are further configured to hold the input/output pin at approximately the voltage potential using a second current. In one embodiment, the driver means may comprise a driver unit for driving the input/output pin to the voltage potential, a bus hold circuit for holding the input/output pin at the voltage potential and a control unit connected to the driver unit and the bus hold circuit. The control unit may activate and deactivate the driver unit and the bus hold circuit.

Method and circuit for preventing and/or inhibiting contention in a

A method of limiting or translating the voltages of input signals, and of generating output signals such that the input's high state and low state differ by a different voltage than the output's high and low state. The present invention also teaches a system comprising a level translator circuit having level translators controlled by an operational amplifier or by a Zener diode that regulates the voltage level on one side of the translators, the other side of the translators being regulated by an external power supply. The operational amplifier or Zener diode, in some embodiments of the present invention, ensures that the second side of the level translators are limited to a given reference voltage. Often, a resistor is connected to the Zener diode or to the output of the operational amplifier, and in some embodiments a resistor-capacitor network removes higher-frequency components from the voltage supply. The invention includes a system level embodiment, in which the voltage level translators protect a memory and bus from voltage levels that would otherwise cause damage.

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San Jose, CA, United States of America

Mathew R Arcoleo