Intel Corporation

Mathew Nevin

Subramaniam M Maiyuran

Jorge E Parra

Ashutosh Garg

Shubra Marwaha

Shubh Shah

An apparatus to facilitate acceleration of matrix multiplication operations. The apparatus comprises a systolic array including matrix multiplication hardware to perform multiply-add operations on received matrix data comprising data from a plurality of input matrices and sparse matrix acceleration hardware to detect zero values in the matrix data and perform one or more optimizations on the matrix data to reduce multiply-add operations to be performed by the matrix multiplication hardware.

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Fair Oaks, CA, United States of America

Mathew Nevin