Micron Technology Incorporated

Mathew L Adsitt

Christophe J Chevallier

Vinod C Lakhani

A memory system including a non-volatile flash memory and a method for simultaneously selecting a plurality of memory blocks are disclosed. The memory system is organized into multiple main blocks each having multiple smaller blocks, emulating a disk drive. Control lines activate a number of modes. In a first mode, high-order address lines select only one block, while in a second mode, user-specified multiple blocks are selected. Blocks are selected by loading registers with selection bits or by using some of the address lines directly as selection bits. Each bit specifies one of the blocks, and each bit is independent of the others. The memory system also includes a predecoder and a controller which controls the predecoder and the registers so as to select at least two blocks of memory cells. In a third mode, all of the blocks are selected, and in a fourth mode, all blocks are deselected. Selecting multiple blocks allows simultaneous erasing, writing, and reading of multiple bytes stored in the memory.

Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure

Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous reading writing or erasure

A memory system including an array of memory cells and a predecoding circuit operable to assert multiblock selection bits (for selecting two or more blocks of the cells simultaneously for simultaneous access) in response to control signals, and a method implemented by such a system, are disclosed. Preferably, the predecoding circuit is operable in a selected one of a first mode in which it asserts single block selection bits in response to address bits (each set of address bits determining one or more cells in a single block of the array) and a second mode in which it asserts multiblock selection bits stored in registers in response to control signals. In a write mode of one embodiment, each set of address bits is associated with a data byte to be written to cells in one row of one block, each set of multiblock selection bits is associated with cells in a row of each of two or more blocks, and the system writes the same data byte to multiple sets of cells (each set of cells in a different block) in response to each set of multiblock selection bits. Preferably, the predecoding circuit asserts a selected one of several different sets of multiblock selection bits in response to each of several different sets of control signals. This allows selection of multiple blocks of cells for simultaneous erasure.

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Boise, ID, United States of America

Mathew L Adsitt