Intel Corporation

Tahoe Research, Ltd.

Mathew J Manusharow

Mihir K Roy

Krishna Bharath

Adel A Elsherbini

Aleksandar Aleksov

Feras Eid

William J Lambert

Ravi Kiran Nalla

Yidnekachew S Mekonnen

Debendra Mallik

Harold Ryan Chase

Mark S Hlad

Henning Braunisch

Zhiguo Qian

Jonathan Rosenfeld

Chia-Pin Chiu

Zhichao Zhang

Javier Soto Gonzalez

Suddhasattwa Nad

Meizi Jiao

Javier Soto

Yikang Deng

Telesphor Kamgaing

Robert L Sankman

Kemal Aygun

Andrew Paul Collins

Pramod Malatkar

Brandon M Rawlings

Dustin P Wood

Jianyong Xie

Michael J Hill

Daniel N Sobieski

Siddharth Kulasekaran

Edward Allyn Burton

Sanka Ganesan

Wilfred Gomes

Kaladhar Radhakrishnan

Ram S Viswanath

Digvijay Ashokkumar Raorane

Rajasekaran Swaminathan

Sriram Srinivasan

Richard J Dischler

Thomas A Boyd

Jeff C Morriss

Beomseok Choi

Drew W Delaney

Ajit V Sathe

Mohiuddin M Mazumder

Yu Zhang

Yu Amos Zhang

Eduard Roytman

Leigh E Wojewoda

Anne Augustine

Sridhar Narasimhan

Haifa Hariri

Sung-Won Moon

Nathan Fritz

Embodiments disclosed herein include coreless interposers with embedded inductors. In an embodiment, a coreless interposer comprises a plurality of buildup layers, where electrical routing is provided in the plurality of buildup layers. In an embodiment, the coreless interposer further comprises an inductor embedded in the plurality of buildup layers. In an embodiment, the inductor comprises a magnetic shell, and a conductive lining over an interior surface of the magnetic shell.

Magnetic core inductors in interposer

Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via. Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.

High density interconnect device and method

An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (EMIB) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate.

Size and efficiency of dies

Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.

High performance integrated RF passives using dual lithography process

Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.

Low loss and low cross talk transmission lines with stacked dielectric layers for forming stubs of different thickness or for forming a coaxial line

An apparatus is provided which comprises: one or more first conductive contacts on a first substrate surface, one or more second conductive contacts on a second substrate surface opposite the first substrate surface, a core layer comprising glass between the first and the second substrate surfaces, and one or more thin film capacitors on the glass core conductively coupled with one of the first conductive contacts and one of the second conductive contacts, wherein the thin film capacitor comprises a first metal layer on a surface of the glass core, a thin film dielectric material on a surface of the first metal layer, and a second metal layer on a surface of the thin film dielectric material. Other embodiments are also disclosed and claimed.

Integrated thin film capacitors on a glass core substrate

Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.

Helical plated through-hole package inductor

An apparatus includes a substrate, one or more integrated circuit dies on the substrate, and a stiffener affixed to the substrate. One or more sections of the stiffener may includes a magnetic material. The apparatus further includes an inductive circuit element comprising one or more conductive structures wrapped around the magnetic material. In some examples where a first coil is wrapped around a first section of the stiffener, and a second coil is wrapped around a second section of the stiffener, current supplied to the first coil generates at the second coil a current that is further transmitted to the one or more semiconductor dies.

Apparatus and system with package stiffening magnetic inductor core and methods of making the same

Embodiments include a microelectronic device package structure having an inductor within a portion of a substrate, wherein the inductor is at least partially embedded within the substrate. One or more thermal vent structures extend through at least one of the substrate or a board attached to the substrate. The one or more thermal vent structures provide a thermal pathway for cooling for the inductor.

Package structure having substrate thermal vent structures for inductor cooling

Low loss and low cross talk transmission lines having l-shaped cross sections

Growing community of inventors

Phoenix, AZ, United States of America

Mathew J Manusharow