Intel Corporation

Mathew B Nazareth

Varghese George

Sanjeev S Jahagirdar

Kedar Mangrulkar

Inder M Sodhi

Hari Giduturi

Jahanshir J Javanifard

George L Geannopoulos

David E Duarte

Usman Mughal

John B Conrad

Tanveer R Khondker

Venkatesh Prasanna

Jason C Stinson

Edwin R Lilya

Mark A Newman

Tanjeer R Khondker

Islam Derhalli

An embodiment of the present invention is a technique for thermal sensing. A sensing structure generates a response according to a local temperature at a first location on a die. A sensor core coupled to the sensing structure via routing lines to provide a measurement of the local temperature from the response. The sensor core is located at a second location remote to the first location and is powered by an analog supply voltage source located in a vicinity of the second location.

Accurate on-die temperature measurement using remote sensing

A method and apparatus automatically transferring to an enhanced low-power state of a processor is disclosed. In one embodiment, either all or a portion of a processor core clock distribution grid may be powered down in these enhanced low-power states. In one embodiment, the processor may operate in a reduced power supply voltage and operate at a reduced frequency during these enhanced low-power states. In one embodiment, a portion of the clock distribution grid may be left on to support snoop operations at a reduced frequency.

Method and apparatus for improved reliability and reduced power in a processor by automatic voltage control during processor idle states

An embodiment of the present invention includes a standby clock generator and a selector. The standby clock generator generates a standby clock synchronous to a core clock. The core clock is generated by a core clock generator during a normal operation mode. The core clock generator stops the core clock during a frequency transition. The selector generates a processor clock from the standby clock during the frequency transition from the normal operation mode according to a selector control signal.

Maintaining processor execution during frequency transitioning

According to some embodiments, a potential clock signal is selected based on a comparison between a selected first clock signal and a second clock signal.

Selecting a first clock signal based on a comparison between a selected first clock signal and a second clock signal

A fingered capacitor in an integrated circuit. A first capacitor element is formed in a first layer of an integrated circuit (IC) die. The first capacitor element includes a positive plate and a negative plate. Each of the positive and negative plates of the first capacitor element has a plurality of fingers interdigitated with the fingers of the other of the positive and negative plates of the first capacitor element. The fingers are separated by a dielectric. The interdigitated fingers cooperate to generate fringe capacitance between neighboring fingers. A plurality of capacitor elements having interdigitated fingers can be provided in adjacent layers of the IC die.

Fingered capacitor in an integrated circuit

A circuit to vary a frequency of an input clock is disclosed. The circuit includes a delay generator to generate at least two delayed clocks from the input clock and a select circuit coupled to receive the at least two delayed clocks and provide an output clock from one of the at least two delayed clocks. The select circuit switches the output clock from the one of the at least two delayed clocks to the other of the at least two delayed clocks on a first edge.

Method and apparatus for varying a clock frequency on a phase by phase

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Rancho Cordova, CA, United States of America

Mathew B Nazareth