Cadence Design Systems, Inc.

Mateus Paiva Fogaça

Mehmet Can Yildiz

Wing-Kai Chow

Gracieli Posser

Zhuo Li

Various embodiments provide for pin access location generation for one or more cells of a circuit design, which may be part of electronic design automation (EDA). Some embodiments facilitate pin access location generation by generating and using multiple graphs, which enable such embodiments to ensure that neighbor pins are not missed and to check for design rule violations.

Cell-based pin access location generation

Various embodiments provide for detecting and modeling vias of a circuit design during global routing, which may be part of electronic design automation (EDA). In particular, various embodiments described herein detect and model a big via during a global routing process, which can help mitigate or avoid minimum spacing violations by big vias.

Detecting and modeling via during global routing

Various embodiments provide for routing a circuit design based on adjusting a routing demand. More specifically, some embodiments implement routing demand smoothing of a grid cell, routing overflow spreading of a grid cell, or some combination of both prior to detailed routing of a circuit design, which can result in improved detailed routing over conventional routing techniques.

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Porto Alegre, Brazil

Mateus Paiva Fogaça