Cadence Design Systems, Inc.

Mateus Gonçalves Silva

Thiago Radicchi Roque

The present disclosure relates to a computer-implemented method for performing a reset sequence simulation in an electronic design. The method may include receiving, using at least one processor, a sequence file including at least one reset, input and cycle value. The method may further include sampling during a first set of cycles set forth in the sequence file and detecting stability at a time point during a first set of cycles. The method may also include bypassing sampling during one or more remaining time points of the first set of cycles, sampling during a second set of cycles set forth in the sequence file and detecting stability at a time point during a second set of cycles.

Growing community of inventors

Belo Horizonte, Brazil

Mateus Gonçalves Silva