Mellanox Technologies, Ltd.

Matan Groen

Hananel Faig

Chen Gaist

David (Dima) Rohlin

In some disclosed embodiments, a Decision Feedback Equalizer (DFE) processes multiple symbols in parallel using a novel architecture that avoids violating a timing constraint. The DFE comprises Feed-Back (FB) filters that can be configured to equalizing nonlinear phenomena. Using a Look-Up Table (LUT)-based implementation, the FB filters may implement complex nonlinear functions at low hardware complexity, low latency and low power consumption. A LUT-based implementation of the FB filter supports adaptive FB filtering to changing channel conditions by updating LUT content.

Parallel decision feedback equalizer partitioned for high throughput

A method for implementing an efficient clock recovery for multilane high-speed Serializer/Deserializer (SerDes) system having M interleaved lanes, has a non-recursive architecture.

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Kfar Saba, Israel

Matan Groen