Oki Electric Industry Co., Ltd.

Oki Data Corporation

Masumi Koizumi

Masaharu Nobori

Hiroyuki Fujiwara

Masumi Taninaka

Yukio Nakamura

Tsutomu Nomoto

Hiroshi Hamano

Makoto Ishimaru

Aya Yamanaka

Mitsuhiko Ogihara

Akihiko Nishiki

Ichimatsu Abiko

Kazuya Ohkawa

Takao Kusano

Shinya Jyumonji

Susumu Ozawa

Yichao Jiang

A composite semiconductor device is formed of a semiconductor wafer having a plurality of device-forming areas in which semiconductor elements are formed and dicing areas defined between the device-forming areas, and is formed by dicing the semiconductor wafer at the dicing areas. The composite semiconductor device includes a semiconductor substrate, and a plurality of wiring layers layered on the semiconductor substrate. The wiring layers include at least conductive films. Connecting portions are formed to connect the wiring layers with each other in a layering direction of the wiring layers. Each of the connecting portions is disposed on the device-forming area side with respect to a dicing position defined in the dicing area.

Composite semiconductor device, print head and image forming apparatus

An LED array includes a semiconductor substrate and a plurality of first LED portions formed integrally on a surface of the semiconductor substrate. The first LED portions emit light of a predetermined color. The LED array includes a plurality of second LED portions fixed to the semiconductor substrate and are disposed corresponding to the first LED portions. The second LED portions emit light whose color is different from the first LED portions. The second LED portions are so disposed that active layers of the second LED portions are substantially at the same height as active layers of the first LED portions.

LED array, LED head and image recording apparatus

A light-emitting-element array has a semiconductor layer formed on a current-blocking layer. Light-emitting elements are formed in the semiconductor layer by diffusion of an impurity of a different conductive type. An isolation trench divides the semiconductor layer into a first region and a remaining region, and divides the array of light-emitting elements into segments disposed alternately in these two regions, each segment preferably including one or two light-emitting elements. A first shared interconnecting pad is electrically coupled to the light-emitting elements in the first region by electrical paths not crossing the isolation trench. A second shared interconnecting pad is electrically coupled to light-emitting elements in the remaining semiconductor region by electrical paths crossing the isolation trench. The array can then be driven by a number of separate interconnecting pads equal to half the number of the light-emitting elements.

Light-emitting-element array

An array of semiconductor circuit elements such as light-emitting elements includes a semiconductor layer partially covered by a dielectric film. A first interconnecting pad such as a wire-bonding pad is electrically coupled by conductive paths passing through the semiconductor layer to electrodes of a first group of semiconductor circuit elements formed in the semiconductor layer. A second interconnecting pad such as a wire-bonding pad, formed on the dielectric film, is electrically coupled to electrodes of a second group of semiconductor circuit elements formed in the semiconductor layer by conductive paths insulated from the semiconductor layer by the dielectric film. The second conductive paths cross the first conductive paths at points at which the first conductive paths pass through the semiconductor layer, so that only a single layer of metal interconnecting lines is needed.

Semiconductor array device with single interconnection layer

An opto-electronic device has a diffusion area of one conductive type formed in a semiconductor substrate of another conductive type, an ohmic contact layer making contact with the diffusion area, and an electrode making contact with the ohmic contact layer. The diffusion area is formed by solid-phase diffusion. The same mask is used to define the patterns of both the diffusion source layer and the ohmic contact layer, so that the ohmic contact layer is self-aligned with the diffusion area.

Opto-electronic device with self-aligned ohmic contact layer

A light-emitting array and its driving circuitry are integrated into a single device. The driving circuitry is formed in a semiconductor substrate and has an array of output terminals on a surface of the substrate. Organic electroluminescent elements are formed directly over the output terminals, in electrical contact with the output terminals. The electroluminescent elements are driven by direct current. An optical head assembly has one or more of these light-emitting arrays mounted on a printed circuit board.

Organic electroluminescent light-emitting array and optical head assembly

An alignment mark on a light-emitting diode (LED) array chip is formed together with the light-emitting areas of the diodes in the array, by use of a combined mask having a first part and a second part. An impurity is introduced through windows in the first part to form the light-emitting areas. Next the windows are covered with an etching resist, and the chip substrate is etched to create a topographic relief feature defined by the second part of the mask. This topographic relief feature is used as an alignment mark. When LED array chips having these alignment marks are mounted on a supporting surface, they are aligned by recognizing patterns of light reflected from the topographic relief, thereby detecting the positions of the alignment marks.

LED array alignment mark, method and mask for forming same, and LED

An end facet light emitting type LED has a slanted light emitting side wall relative to a substrate surface. A method for manufacturing end facet light emitting type light emitting devices prevents the pn-junction regions of the devices from being damaged while a semiconductor wafer is diced to separate light emitting devices from one another. A recess is formed on the semiconductor wafer having a depth which is deeper than the pn-junction. A portion to be cut during dicing of the wafer is vertically and horizontally separated from the pn-junction regions, so that if cracks occur when the wafer is diced, the cracks do not affect the light emitting characteristics of the devices.

End face light emitting type light emitting diode

An end face light-emitting-type LED has a first-conductive-type semiconductor substrate and a second-conductive-type diffusion region formed on a first surface of the first-conductive-type semiconductor substrate so as to have a depth within a predetermined value. The first-conductive-type semiconductor substrate has a second surface which meets the first surface at a predetermined angle with the first surface. A junction between the first-conductive-type semiconductor substrate and the second-conductive-type diffusion region includes an inclined portion with regard to the first surface in the vicinity of an edge portion of the junction which is on a side of the second surface, and light emerges from the junction via the second surface.

End face light-emitting-type LED, end face light-emitting-type LED array

In a fabricating method for an end face light emitting type LED array, p-type regions are formed by diffusing impurities into portions of a semiconductor substrate, using a diffusion prevention film as a mask. Subsequently, using the diffusion prevention film as a mask again, the semiconductor substrate is etched to form a concave portion therein so that light-emission end faces are formed on a side of the concave portion. With this arrangement, a positional misalignment between the p-type regions and the light-emission end faces is prevented.

Method of fabricating an end face light emitting type light-emitting

A pn-junction element is formed in a compound semiconductor substrate by depositing an aluminum-nitride film on the surface of the substrate, patterning the aluminum-nitride film to form a diffusion mask, depositing a diffusion source film on the diffusion mask, diffusing an impurity from the diffusion source film into the substrate, and removing the diffusion source film with buffered hydrofluoric acid. Electrode lines can then be formed directly on the aluminum-nitride diffusion mask, which is not etched by buffered hydrofluoric acid.

Diffusion mask and fabrication method for forming pn-junction elements

A TFT matrix for an active matrix display panel has a plurality of TFTs arranged in rows and columns to form a matrix array. Each of the TFT has a control electrode on a dielectric substrate, a first insulator film formed on the control electrode, a second insulator film formed on the first insulator film, a-Si semiconductor layer formed on the second insulator film, and first and second (drain and source) electrodes formed on the a-Si semiconductor layer. The matrix has a plurality of transparent electrodes that contact the second electrodes, row interconnection layers interconnecting the control electrodes of the TFTs of the respective rows, and column interconnection layers interconnecting the first electrodes of the TFTs of the respective columns. The control electrodes and the row interconnection layers (gate electrodes) are made of an alloy of tantalum with tungsten, nickel, cobalt, rhodium, or iridium. The first insulator is formed by anodizing the surface of the gate electrode. The gate electrode has low resistance, improving the quality of the display without impairing insulation performance.

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Tokyo, Japan

Masumi Koizumi