Intel Corporation

Qualcomm Incorporated

Masud Kamal

Keng L Wong

Suresh Kumar Venkumahanti

Paul Bassett

Chee How Lim

Jian Shen

Usman Mughal

Kent R Callahan

Lin Wang

The present disclosure includes a multi-threaded processor that includes a first register file associated with a first thread and a second register file associated with a second thread. At least one hardware resource is shared by the first and second register files. In addition, the first thread may have a pipeline access position that is non-sequential to the second thread. A method of accessing a plurality of register files is also disclosed. The method includes reading data from a first register file while concurrently reading data from a second register file. The first register file is associated with a first instruction stream and the second register file is associated with a second instruction stream. The first instruction stream is sequential to the second instruction stream in an execution pipeline of a processor, and the first register file is in a non-adjacent location with respect to the second register file.

Register file system and method for pipelined processing

A lock detector system which operates adaptively based on a frequency of operation. Different lock windows are defined for different frequencies of operation and are automatically formed based on the controlled signal that is used to drive the voltage controlled oscillator of the phase locked loop.

Variable lock window for a phase locked loop

Growing community of inventors

Pflugerville, TX, United States of America

Masud Kamal