Advanced Micro Devices Corporation

Massud Aminpur

Scott D Luning

David Donggang Wu

Kay Hellig

Kai Frohberg

Michael P Duane

Matthias Schaller

William R Roche

Thomas Werner

Hartmut Ruelke

Joerg Hohage

Martin Mazur

Gert Burbach

Christian Zistl

Phillip E Crabtree

Karen L E Turnqest

Roberto Klingler

By providing a contact etch stop layer, the stress in channel regions of different transistor types may be effectively controlled, wherein tensile and compressive stress portions of the contact etch stop layer may be obtained by well-established processes, such as wet chemical etch, plasma etch, ion implantation, plasma treatment and the like. Hence, a significant improvement in transistor performance may be obtained while not significantly contributing to process complexity.

Technique for creating different mechanical stress in different channel regions by forming an etch stop layer having differently modified intrinsic stress

During the formation of a transistor element, sidewalls spacers are removed or at least partially etched back after ion implantation and silicidation, thereby rendering the mechanical coupling of a contact etch stop layer to the underlying drain and source regions more effective. Hence, the mechanical stress may be substantially induced by the contact etch step layer rather than by a combination of the spacer elements and the etch stop layer, thereby significantly facilitating the stress engineering in the channel region. By additionally performing a plasma treatment, different amounts of stress may be created in different transistor devices without unduly contributing to process complexity.

Technique for controlling mechanical stress in a channel region by spacer removal

A method for fabricating sidewall spacers in the manufacture of an integrated circuit device is disclosed. A dielectric spacer layer is formed over the semiconductor substrate. The dielectric spacer layer is etched prior to forming a layer subsequent to the dielectric layer, to form an L-shaped spacer. In another embodiment, a structure is formed on a substrate, the structure having a sidewall portion that is substantially orthogonal to a surface of the substrate. A dielectric layer is formed over the substrate. A spacer is formed over a portion of the dielectric layer and adjacent to the sidewall portion of the structure, wherein at least a portion of the dielectric layer over the substrate without an overlying oxide spacer is an unprotected portion of the dielectric. At least a part of the unprotected portion of the dielectric layer is removed. An intermediate source-drain region can be formed beneath a portion of the L-shaped spacer by controlling the thickness and/or the source drain doping levels.

System for forming a semiconductor device and method thereof

The anisotropic etch process for forming circuit elements such as a gate electrode is accomplished by using a hard mask instead of a resist feature, thereby avoiding a complex resist trim process when critical dimensions are required, which are well below the resolution of the involved photolithography. Moreover, the critical dimension may be adjusted by means of a deposition process rather than by a resist trim process.

Technique for forming a gate electrode by using a hard mask

The present invention is directed to a semiconductor device having a gate electrode includes of a plurality of sidewalls, each having a recess formed therein. The present invention is also directed to a method of forming a semiconductor device. In one illustrative embodiment, the method comprises forming a layer of dopant material in a layer of polysilicon and etching the layer of polysilicon to define a gate electrode having a plurality of sidewalls, each of which have a recess formed therein.

Method of forming a gate electrode on a semiconductor device and a device incorporating same

A semiconductor device manufacturing method is provided where a device structure is formed on top of a wafer that comprises a backside semiconductor substrate, a buried insulator layer and a top semiconductor layer. Then, an etch stop layer is formed upon the wafer that carries the device structure, and a window is formed in the etch stop layer. Further, a dielectric layer is formed upon the etch stop layer that has the window. Then, a first contact hole through the dielectric layer and the window down to the backside semiconductor substrate is simultaneously etched with at least one second contact hole through the dielectric layer down to the device structure. The wafer may be a silicon-on-insulator (SOI) wafer, and the etch stop layer and the dielectric layer may be formed by depositing silicon oxynitride and tetraethyl orthosilicate (TEOS), respectively. The device structure may be a CMOS transistor structure.

Simultaneous formation of device and backside contacts on wafers having a buried insulator layer

The effect of resist poisoning may be eliminated or at least substantially reduced in the formation of a low-k metallization layer, in that a nitrogen-containing barrier/etch stop layer is provided with a significantly reduced nitrogen concentration at an interface in contact with said low-k dielectric material. Consequently, diffusion of nitrogen and nitrogen compounds in vias formed in said low-k dielectric layer is significantly suppressed, so that in a subsequent photolithographic step, interaction of nitrogen and nitrogen compounds with the photoresist is remarkably reduced.

Barrier layer for a copper metallization layer including a low-k dielectric

A method for forming an integrated circuit includes etching a first opening to a first depth in a dielectric material over a semiconductor device on a first semiconductor substrate and etching a second opening to a second depth in the dielectric material over the first semiconductor substrate. The first and second openings are differently sized to respectively etch to the first and second depths in about the same time due to etch lag. The first and second openings are filled with conductive material.

Method of manufacturing multi-level contacts by sizing of contact sizes in integrated circuits

A method is provided, the method including forming a gate dielectric above a substrate layer, and forming a gate conductor above the gate dielectric. The method also includes forming at least one dielectric isolation structure in the substrate adjacent the gate dielectric.

Channel isolation using dielectric isolation structures

Various circuit structures incorporating masks and anti-reflective coatings and methods of fabricating the same are provided. In one aspect, a circuit structure is provided that includes a substrate and a first photosensitive film on the substrate. The first photosensitive film is photosensitive to a first electromagnetic spectrum and anti-reflective of a second electromagnetic spectrum that differs from the first electromagnetic spectrum. A second photosensitive film is on the first photosensitive film. The second photosensitive film is photosensitive to the second electromagnetic spectrum whereby exposure by the second electromagnetic spectrum will activate the second photosensitive film but not the first photosensitive film and exposure by the first electromagnetic spectrum will activate unmasked portions of the first photosensitive film. The first photosensitive film doubles as an anti-reflective coating that may be patterned anisotropically using lithographic techniques.

Photosensitive bottom anti-reflective coating

The present invention is directed to a method of forming halo implants in a semiconductor device. In one illustrative embodiment, the method comprises forming a gate electrode above a surface of a semiconducting substrate, and forming a hard mask layer above the gate electrode and the substrate. The method further comprises patterning the hard mask layer to define an opening in the hard mask layer, and performing an angled implantation process through the opening in the hard mask to introduce dopant atoms into the substrate under at least a portion of the gate electrode.

Method of forming a hard mask for halo implants

A method is provided, the method including forming a gate dielectric above a surface of the substrate, forming the conductive gate structure above the gate dielectric, the conductive gate structure having an edge region, and forming a source/drain extension (SDE) adjacent the conductive gate structure. The method also includes forming a dopant-depleted-SDE region in the substrate under the edge region of the conductive gate structure.

Semiconductor device and method for lowering miller capacitance by modifying source/drain extensions for high speed microprocessors

The present invention is directed to a method of forming halo implants in a semiconductor device. In one illustrative embodiment, the method comprises forming a structure above a semiconducting substrate, forming a layer of photoresist above the structure and the substrate, and positioning the substrate in an exposure tool that has a light source and a focal plane. The method further comprises positioning the surface of the layer of photoresist in an exposure plane that is different from the focal plane of the exposure tool, exposing the photoresist to the light source of the exposure tool while the surface of the photoresist is in the exposure plane, and developing the layer of photoresist to define an opening in the layer of photoresist around the structure on the substrate.

Method of reducing photoresist shadowing during angled implants

With standard DUV lithography technology it is not easy to achieve MOS transistor gates in sub-100 nm range. With the method of trim-etching in HI/O plasmas there is an opportunity to use the current lithography tools, to reduce the dimensions of the resist feature, and to achieve sub-100 nm MOS transistor gates for advanced devices. The method of trim-etching in HI/O plasmas delivers another factor to control the critical dimension of the MOS devices very accurately. Therefore, this invention helps to significantly reduce the total cost for manufacturing small MOS devices with a critical dimension in the sub-100 nm range.

Method of producing a semiconductor device using feature trimming

A method is provided, the method including forming a gate dielectric layer above a substrate layer, forming a gate conductor layer above the gate dielectric layer, forming a first hard mask layer above the gate conductor layer, and forming a second hard mask layer above the first hard mask layer. The method also includes forming a trimmed photoresist mask above the second hard mask layer, and forming a patterned hard mask in the second hard mask layer using the trimmed photoresist mask to remove portions of the second hard mask layer, the patterned hard mask having a first dimension. The method further includes forming a selectively etched hard mask in the first hard mask layer by removing portions of the first hard mask layer adjacent the patterned hard mask, the selectively etched hard mask having a second dimension less than the first dimension, and forming a gate structure using the selectively etched hard mask to remove portions of the gate conductor layer above the gate dielectric layer.

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Dresden, Germany

Massud Aminpur