Fujitsu Corporation

University of Southern California

Other

Seeqc Inc.

Massoud Pedram

Farzan Fallah

Yazdan Aghaghiri

Behnam Amelifard

Ehsan Pakbaznia

Oleg A Mukhanov

Naveen Katam

Ghasem Pasandi

Ali Iranli

Afshin Abdollahi

An SFQ circuit system includes at least one SFQ block having a plurality of SFQ logic gates. Characteristically, at least a portion of the SFQ logic gates are arranged in series. The SFQ circuit system includes a timing system configured to provide a first set of inputs and collect a first set of outputs of the at least one SFQ block at a rate defined by a slow clock frequency while the SFQ logic gates are clocked at a fast clock frequency. Advantageously, the rate is sufficiently slow to allow the first set of inputs to propagate through all levels of the SFQ logic gates to produce the first set of outputs of the at least one SFQ block without colliding with a second set of inputs to the at least one SFQ block.

Efficient pipelined architecture for superconducting single flux quantum logic circuits utilizing dual clocks

A superconducting field programmable gate array (SuperFPGA) apparatus for implementing a superconducting electronic circuit includes a superconducting logic core that includes a plurality of superconducting single flux quantum configurable logic blocks having regular Josephson junctions and inductors that are interconnectible to each other and to input/output terminals of the superconducting electronic circuit. The SuperFPGA apparatus also includes a superconducting routing network, a zero-static-power dissipation biasing network, magnetic Josephson junctions, and a magnetic Josephson junction programming layer.

Superconducting magnetic field programmable gate array

An embodiment of the present invention is directed to a method for determining a pixel transformation function that maximizes backlight dimming while maintaining a pre-specified distortion level. The method includes determining a minimum dynamic range of pixel values in a transformed image based on an original image and the pre-specified distortion level and determining the pixel transformation function. The pixel transformation function takes a histogram of the original image to a uniform distribution histogram having the minimum dynamic range.

Dynamic backlight scaling for power minimization in a backlit TFT-LCD

In one embodiment, a circuit includes a first row of circuit blocks that are each connected to a supply directly and to ground via a first sleep transistor. A connection between the first circuit block and the first sleep transistor is a virtual ground node. The circuit includes a second row of circuit blocks that are each connected to ground directly and to the supply via a second sleep transistor. A connection between the second circuit block and the second sleep transistor is a virtual supply node. The circuit includes a transmission gate (TG) or pass transistor connecting the virtual ground nodes to the virtual supply nodes to enable charge recycling between circuit blocks in the first row and circuit blocks in the second row during transitions by the circuit from active mode to sleep mode, from sleep mode to active mode, or both.

Sizing and placement of charge recycling (CR) transistors in multithreshold complementary metal-oxide-semiconductor (MTCMOS) circuits

In one embodiment, a method for power mode transition in a multi-threshold complementary metal oxide semiconductor (MTCMOS) circuit includes clustering logic cells in the circuit to a number of logic clusters and optimizing wake-up times of the logic clusters to reduce a total turn-on time of the circuit while keeping below a predetermined threshold a sum of currents flowing from the circuit to ground, a sum of currents flowing from a supply voltage to the circuit, or both during a transition by the circuit from sleep mode to active mode.

Power mode transition in multi-threshold complementary metal oxide semiconductor (MTCMOS) circuits

In one embodiment, a memory block includes one or more bit lines that each include two or more cells. Each cell in each bit line has a distance from a sense amplifier coupled to the bit line, and each of one or more of the cells in each of one or more of the bit lines has a delay particularly set according to the distance of the cell from the sense amplifier coupled to the bit line.

Setting threshold voltages of cells in a memory block to reduce leakage in the memory block

A method of forming a memory cell includes coupling a first transistor between a supply rail of a memory cell and a node operable to accept a supply voltage. The method further includes coupling a second transistor between a ground rail of the cell and a node operable to accept a ground. In one embodiment, the method includes forming the cell to accept selectively applied external voltages, wherein the external voltages are selected to minimize leakage current in the cell. In another embodiment, the method includes forming at least one of the first and the second transistors to have a channel width and/or a threshold voltage selected to minimize a total leakage current in the cell.

PG-gated data retention technique for reducing leakage in memory cells

In one embodiment, a circuit includes a first circuit block connected to ground via a first sleep transistor, a virtual ground node between the first circuit block and the first sleep transistor, a second circuit block connected to a supply via a second sleep transistor, and a virtual supply node between the second circuit block and the second sleep transistor. The circuit also includes a transmission gate (TG) or a pass transistor connecting the virtual ground node to the virtual supply node to enable charge recycling between the first circuit block and the second circuit block during transitions by the circuit between active mode and sleep mode.

Recycling charge to reduce energy consumption during mode transition in multithreshold complementary metal-oxide-semiconductor (MTCMOS) circuits

A method for reducing transitions on a bus is provided that includes receiving an input trace and constructing a Markov source correlating to the input trace. The method also includes identifying an encoding technique, which can either minimize or maximize an objective function associated with the input trace.

System and method for identifying optimal encoding for a given trace

An instruction-set-aware method for reducing transitions on an irredundant address bus comprises receiving a first address for communication to a memory on an irredundant address bus. The method retrieves an instruction from a memory location indicated by the first address, transmits the instruction on a data bus, and determines a category of the instruction. The method predicts a second address based, at least in part, on the first address, the instruction, and the category of the instruction.

Reducing transitions on address buses using instruction-set-aware system and method

An encoder and decoder provide coding of information communicated on buses. The encoder and decoder may use various combinations of techniques to reduce switching activity on an address bus.

System and method for reducing transitions on address buses

An encoder and decoder provide coding of information communicated on busses. The encoder and decoder may use various combinations of techniques to reduce switching activity on an address bus.

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Beverly Hills, CA, United States of America

Massoud Pedram